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ltc 6804 -1/ ltc 6804 -2 1 680412f for more information www.linear.com/LTC6804-1 typical application features description multicell battery monitors the lt c ? 6804 is a 3rd generation multicell battery stack monitor that measures up to 12 series connected battery cells with a total measurement error of less than 1.2mv. the cell measurement range of 0v to 5v makes the ltc6804 suitable for most battery chemistries. all 12 cell voltages can be captured in 290s, and lower data acquisition rates can be selected for high noise reduction. multiple ltc6804 devices can be connected in series, permitting simultaneous cell monitoring of long , high volt - age battery strings. each ltc6804 has an isospi interface for high speed, rf-immune, local area communications. using the LTC6804-1, multiple devices are connected in a daisy-chain with one host processor connection for all devices. using the ltc6804-2, multiple devices are con- nected in parallel to the host processor, with each device individually addressed. additional features include passive balancing for each cell, an onboard 5v regulator, and 5 general purpose i/o lines. in sleep mode, current consumption is reduced to 4a. the ltc6804 can be powered directly from the battery , or from an isolated supply. l, lt , lt c , lt m , linear technology and the linear logo are registered and isospi is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. total measurement error vs temperature of 5 typical units applications n measures up to 12 battery cells in series n stackable architecture supports 100s of cells n built-in isospi? interface: 1 mbps isolated serial communications uses a single twisted pair, up to 100 meters low emi susceptibility and emissions n 1.2 mv maximum total measurement error n 290 s to measure all cells in a system n synchronized voltage and current measurement n 16- bit delta-sigma adc with frequency programmable 3rd order noise filter n engineered for iso26262 compliant systems n passive cell balancing with programmable timer n 5 general purpose digital i/o or analog inputs: temperature or other sensor inputs configurable as an i 2 c or spi master n 4 a sleep mode supply current n 48- lead ssop package n electric and hybrid electric vehicles n backup battery systems n grid energy storage n high power portable equipment ltc6820 LTC6804-1 mpu ip ? ? ? ? ? ? ? ? spi im ipa ima 680412 ta01a ipb imb LTC6804-1 ima ipa ilp ipb imb LTC6804-1 ima ipb imb ipa 12s1p + + + + + + temperature (c) ?50 measurement error (mv) 1.5 25 680412 ta01b 0 ?1.0 ?25 0 50 ?1.5 ?2.0 2.0 1.0 0.5 ?0.5 75 100 125 cell voltage = 3.3v 5 typical units
ltc 6804 -1/ ltc 6804 -2 2 680412f for more information www.linear.com/LTC6804-1 table of contents features ..................................................... 1 applications ................................................ 1 typical application ........................................ 1 description .................................................. 1 absolute maximum ratings .............................. 3 pin configuration .......................................... 3 order information .......................................... 4 electrical characteristics ................................. 4 pin functions .............................................. 17 block diagram ............................................. 18 operation ................................................... 20 state diagram ......................................................... 20 ltc6804 core state descriptions ........................... 20 isospi state descriptions ....................................... 21 power consumption ............................................... 21 adc operation ........................................................ 21 data acquisition system diagnostics ..................... 26 watchdog and software discharge timer .............. 30 i 2 c/spi master on ltc6804 using gpios .............. 31 serial interface overview ........................................ 34 4-wire serial peripheral interface (spi) physical layer ....................................................................... 35 2-wire isolated interface (isospi) physical layer ... 35 data link layer ....................................................... 41 network layer ........................................................ 41 programming examples ......................................... 52 simple linear regulator ......................................... 56 improved regulator power efficiency ..................... 56 fully isolated power ................................................ 57 reading external temperature probes .................... 57 expanding the number of auxiliary measurements 58 internal protection features .................................... 58 filtering of cell and gpio inputs ............................. 58 cell balancing with internal mosfets ....................... 60 cell balancing with external mosfets ................... 60 discharge control during cell measurements ........ 60 power dissipation and thermal shutdown ............. 61 method to verify balancing circuitry ...................... 61 current measurement with a hall effect sensor ..... 64 current measurement with a shunt resistor .......... 64 using the ltc6804 with less than 12 cells ........... 65 connecting multiple LTC6804-1 on the same pcb ............................................................... 65 connecting a mcu to an LTC6804-1 with an isospi data link ................................................................ 65 configuring the ltc6804-2 in a multi-drop isospi link .............................................................. 65 transformer selection guide .................................. 67 package description ..................................... 71 typical application ....................................... 72 related parts .............................................. 72
ltc 6804 -1/ ltc 6804 -2 3 680412f for more information www.linear.com/LTC6804-1 absolute maximum ratings total supply voltage v + to v C .................................... 75 v input voltage ( relative to v C ) c 0 ......................................................... C0.3 v to 0.3 v c 12 ........................................................ C0.3 v to 75 v c ( n ) ..................................... C0.3 v to min (8 ? n , 75 v ) s ( n ) ..................................... C0.3 v to min (8 ? n , 75 v ) ipa , ima , ipb , imb .................... C0.3 v to v reg + 0.3 v drive pin ................................................ C0.3 v to 7 v all other pins ........................................... C0.3 v to 6 v voltage between inputs ( note 2) c ( n ) to c ( n C 1) ........................................ C0.3 v to 8 v s ( n ) to c ( n C 1) ........................................ C0.3 v to 8 v c 12 to c 8 ............................................... C0.3 v to 25 v c 8 to c 4 ................................................. C0.3 v to 25 v c 4 to c 0 ................................................. C0.3 v to 25 v (note 1) pin configuration current in / out of pins all pins except v reg , ipa , ima , ipb , imb , s ( n ) .. 10 ma ipa , ima , ipb , imb ............................................. 30 ma operating temperature range ltc 6804 i ............................................. C40 c to 85 c ltc 6804 h .......................................... C40 c to 125 c specified temperature range ltc 6804 i ............................................. C40 c to 85 c ltc 6804 h .......................................... C40 c to 125 c junction temperature ........................................... 150 c storage temperature .............................. C65 c to 150 c lead temperature ( soldering , 10 sec ) .................... 300 c LTC6804-1 ltc6804-2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 top view g package 48-lead plastic ssop 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 v + c12 s12 c11 s11 c10 s10 c9 s9 c8 s8 c7 s7 c6 s6 c5 s5 c4 s4 c3 s3 c2 s2 c1 ipb imb icmp ibias sdo (nc)* sdi (nc)* sck (ipa)* csb (ima)* isomd wdt drive v reg swten v ref1 v ref2 gpio5 gpio4 v ? v ?** gpio3 gpio2 gpio1 c0 s1 t jmax = 125c, ja = 55c/w *the function of these pins depends on the connection of isomd isomd tied to v C : csb, sck, sdi, sdo isomd tied to v reg : ima, ipa , nc, nc **this pin must be connected to v C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 top view g package 48-lead plastic ssop 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 v + c12 s12 c11 s11 c10 s10 c9 s9 c8 s8 c7 s7 c6 s6 c5 s5 c4 s4 c3 s3 c2 s2 c1 a3 a2 a1 a0 sdo (ibias)* sdi (icmp)* sck (ipa)* csb (ima)* isomd wdt drive v reg swten v ref1 v ref2 gpio5 gpio4 v ? v ?** gpio3 gpio2 gpio1 c0 s1 t jmax = 125c, ja = 55c/w *the function of these pins depends on the connection of isomd isomd tied to v C : csb, sck, sdi, sdo isomd tied to v reg : ima, ipa , icmp, ibias **this pin must be connected to v C
ltc 6804 -1/ ltc 6804 -2 4 680412f for more information www.linear.com/LTC6804-1 order information electrical characteristics symbol parameter conditions min typ max units adc dc specifications measurement resolution l 0.1 mv/bit adc offset voltage (note 2) l 0.1 mv adc gain error (note 2) l 0.01 0.02 % % total measurement error (tme) in normal mode c(n) to c(n C 1), gpio(n) to v C = 0 0.2 mv c(n) to c(n C 1) = 2.0 0.1 0.8 mv c(n) to c(n C 1), gpio(n) to v C = 2.0 l 1.4 mv c(n) to c(n C 1) = 3.3 0.2 1.2 mv c(n ) to c(n C 1), gpio(n) to v C = 3.3 l 2.2 mv c(n) to c(n C 1) = 4.2 0.3 1.6 mv c(n) to c(n C 1), gpio(n) to v C = 4.2 l 2.8 mv c(n) to c(n C 1), gpio(n) to v C = 5.0 1 mv sum of cells l 0.2 0.75 % internal temperature, t = maximum specified temperature 5 c v reg pin l 0.1 0.25 % v ref2 pin l 0.02 0.1 % digital supply voltage v regd l 0.1 1 % the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. the test conditions are v + = 39.6v, v reg = 5.0v unless otherwise noted. lead free finish tape and reel part marking* package description specified temperature range ltc6804ig-1#pbf ltc6804ig-1#trpbf ltc6804g-1 48-lead plastic ssop C40c to 85c ltc6804hg-1#pbf ltc6804hg-1#trpbf ltc6804g-1 48-lead plastic ssop C40c to 125c ltc6804ig-2#pbf ltc6804ig-2#trpbf ltc6804g-2 48-lead plastic ssop C40c to 85c ltc6804hg-2#pbf ltc6804hg-2#trpbf ltc6804g-2 48-lead plastic ssop C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult lt c marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ltc 6804 -1/ ltc 6804 -2 5 680412f for more information www.linear.com/LTC6804-1 electrical characteristics symbol parameter conditions min typ max units total measurement error (tme) in filtered mode c(n) to c(n C 1), gpio(n) to v C = 0 0.1 mv c(n) to c(n C 1) = 2.0 0.1 0.8 mv c(n) to c(n C 1), gpio(n) to v C = 2.0 l 1.4 mv c(n) to c(n C 1) = 3.3 0.2 1.2 mv c(n) to c(n C 1), gpio(n) to v C = 3.3 l 2.2 mv c(n) to c(n C 1) = 4.2 0.3 1.6 mv c(n) to c(n C 1), gpio(n) to v C = 4.2 l 2.8 mv c(n) to c(n C 1), gpio(n) to v C = 5.0 1 mv sum of cells l 0.2 0.75 % internal temperature, t = maximum specified temperature 5 c v reg pin l 0.1 0.25 % v ref2 pin l 0.02 0.1 % digital supply voltage v regd l 0.1 1 % total measurement error (tme) in fast mode c(n) to c(n C 1), gpio(n) to v C = 0 2 mv c(n) to c(n C 1), gpio(n) to v C = 2.0 l 4 mv c(n) to c(n C 1), gpio(n) to v C = 3.3 l 4.7 mv c(n) to c(n C 1), gpio(n) to v C = 4.2 l 8.3 mv c(n) to c(n C 1), gpio(n) to v C = 5.0 10 mv sum of cells l 0.3 1 % internal temperature, t = maximum specified temperature 5 c v reg pin l 0.3 1 % v ref2 pin l 0.1 0.25 % digital supply voltage v regd l 0.2 2 % input range c(n), n = 1 to 12 l c(n C 1) c ( n C 1) + 5 v c0 l 0 gpio(n), n = 1 to 5 l 0 5 v i l input leakage current when inputs are not being measured c(n), n = 0 to 12 l 10 250 na gpio(n), n = 1 to 5 l 10 250 na input current when inputs are being measured c(n), n = 0 to 12 2 a gpio(n), n = 1 to 5 2 a input current during open wire detection l 70 100 130 a the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. the test conditions are v + = 39.6v, v reg = 5.0v unless otherwise noted.
ltc 6804 -1/ ltc 6804 -2 6 680412f for more information www.linear.com/LTC6804-1 electrical characteristics symbol parameter conditions min typ max units voltage reference specifications v ref1 1st reference voltage v ref1 pin, no load l 3.1 3.2 3.3 v 1st reference voltage tc v ref1 pin, no load 3 ppm/c 1st reference voltage hysteresis v ref1 pin, no load 20 ppm 1st reference long term drift v ref1 pin, no load 20 ppm/khr v ref2 2nd reference voltage v ref2 pin, no load l 2.990 3 3.010 v v ref2 pin, 5k load to v C l 2.988 3 3.012 v 2nd reference voltage tc v ref2 pin, no load 10 ppm/c 2nd reference voltage hysteresis v ref2 pin, no load 100 ppm 2nd reference long term drift v ref2 pin, no load 60 ppm/khr general dc specifications i vp v + supply current (see figure 1: ltc6804 operation state diagram) state: core = sleep, isospi = idle v reg = 0v 3.8 6 a v reg = 0v l 3.8 10 a v reg = 5v 1.6 3 a v reg = 5 v l 1.6 5 a state: core = standby 18 32 50 a l 10 32 60 a state: core = refup or measure 0.4 0.55 0.7 ma l 0.375 0.55 0.725 ma i reg(core) v reg supply current (see figure 1: ltc6804 operation state diagram) state: core = sleep, isospi = idle v reg = 5v 2.2 4 a v reg = 5v l 2.2 6 a state: core = standby 10 35 60 a l 6 35 65 a state: core = refup 0.2 0.45 0.7 ma l 0.15 0.45 0.75 ma state: core = measure 10.8 11.5 12.2 ma l 10.7 11.5 12.3 ma i reg(isospi) additional v reg supply current if isospi in ready/active states note: active state current assumes t clk = 1s, (note?3) ltc6804-2: isomd = 1, r b1 + r b2 = 2k ready l 3.9 4.8 5.8 ma active l 5.1 6.1 7.3 ma LTC6804-1: isomd = 0, r b1 + r b2 = 2k ready l 3.7 4.6 5.6 ma active l 5.7 6.8 8.1 ma LTC6804-1: isomd = 1, r b1 + r b2 = 2k ready l 6.5 7.8 9.5 ma active l 10.2 11.3 13.3 ma ltc6804-2: isomd = 1, r b1 + r b2 = 20k ready l 1.3 2.1 3 ma active l 1.6 2.5 3.5 ma LTC6804-1: isomd = 0, r b1 + r b2 = 20k ready l 1.1 1.9 2.8 ma active l 1.5 2.3 3.3 ma LTC6804-1: isomd = 1, r b1 + r b2 = 20k ready l 2.1 3.3 4.9 ma active l 2.7 4.1 5.8 ma the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. the test conditions are v + = 39.6v, v reg = 5.0v unless otherwise noted.
ltc 6804 -1/ ltc 6804 -2 7 680412f for more information www.linear.com/LTC6804-1 electrical characteristics symbol parameter conditions min typ max units v + supply voltage tme specifications met (note 6) l 11 40 55 v v reg v reg supply voltage tme supply rejection < 1mv/v l 4.5 5 5.5 v drive output voltage sourcing 1a l 5.4 5.2 5.6 5.6 5.8 6.0 v v sourcing 500a l 5.1 5.6 6.1 v v regd digital supply voltage l 2.7 3.0 3.6 v discharge switch on resistance v cell = 3.6v l 10 25 thermal shutdown temperature 150 c v ol(wdt) watchdog timer pin low wdt pin sinking 4ma l 0.4 v v ol(gpio) general purpose i/o pin low gpio pin sinking 4ma (used as digital output) l 0.4 v adc timing specifications t cycle (figure?3) measurement + calibration cycle time when starting from the refup state in normal mode measure 12 cells l 2120 2335 2480 s measure 2 cells l 365 405 430 s measure 12 cells and 2 gpio inputs l 2845 3133 3325 s measurement + calibration cycle time when starting from the refup state in filtered mode measure 12 cells l 183 201.3 213.5 ms measure 2 cells l 30.54 33.6 35.64 ms measure 12 cells and 2 gpio inputs l 244 268.4 284.7 ms measurement + calibration cycle time when starting from the refup state in fast mode measure 12 cells l 1010 1113 1185 s measure 2 cells l 180 201 215 s measure 12 cells and 2 gpio inputs l 1420 1564 1660 s t skew1 (figure 6) skew time. the time difference between c12 and gpio2 measurements, command = adcvax fast mode l 189 208 221 s normal mode l 493 543 576 s t skew2 (figure 3) skew time. the time difference between c12 and c0 measurements, command = adcv fast mode l 211 233 248 s normal mode l 609 670 711 s t wake regulator start-up time v reg generated from drive pin (figure 28) l 100 300 s t sleep watchdog or software discharge timer swten pin = 0 or dcto[3:0] = 0000 l 1.8 2 2.2 sec swten pin = 1 and dcto[3:0] 0000 0.5 120 min t refup (figure?1, figures 3 to 7) reference wake-up time state: core = standby l 2.7 3.5 4.4 ms state: core = refup l 0 ms f s adc clock frequency l 3.0 3.3 3.5 mhz spi interface dc specifications v ih(spi) spi pin digital input voltage high pins csb, sck, sdi l 2.3 v v il(spi) spi pin digital input voltage low pins csb, sck, sdi l 0.8 v v ih(cfg) configuration pin digital input voltage high pins isomd, swten, gpio1 to gpio5, a0 to a3 l 2.7 v v il(cfg) configuration pin digital input voltage low pins isomd, swten, gpio1 to gpio5, a0 to a3 l 1.2 v the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. the test conditions are v + = 39.6v, v reg = 5.0v unless otherwise noted.
ltc 6804 -1/ ltc 6804 -2 8 680412f for more information www.linear.com/LTC6804-1 electrical characteristics symbol parameter conditions min typ max units i leak(dig) digital input current pins csb, sck, sdi, isomd, swten, a0 to a3 l 1 a v ol(sdo) digital output low pin sdo sinking 1ma l 0.3 v isospi dc specifications (see figure 16) v bias voltage on ibias pin ready/active state idle state l 1.9 2.0 0 2.1 v v i b isolated interface bias current r bias = 2k to 20k l 0.1 1.0 ma a ib isolated interface current gain v a 1.6v i b = 1ma i b = 0.1ma l l 18 18 20 20 22 24.5 ma/ma ma/ma v a transmitter pulse amplitude v a = |v ip C v im | l 1.6 v v icmp threshold-setting voltage on icmp pin v tcmp = a tcmp ? v icmp l 0.2 1.5 v i leak(icmp) input leakage current on icmp pin v icmp = 0v to v reg l 1 a i leak(ip/im) leakage current on ip and im pins idle state, v ip or v im = 0v to v reg l 1 a a tcmp receiver comparator threshold voltage gain v cm = v reg /2 to v reg C 0.2v, v icmp = 0.2v to 1.5v l 0.4 0.5 0.6 v/v v cm receiver common mode bias ip/im not driving (v reg C v icmp /3 C 167mv) v r in receiver input resistance single-ended to ipa , ima, ipb, imb l 27 35 43 k isospi idle/ wakeup specifications (see figure 21) v wake differential wake-up voltage t dwell = 240ns l 200 mv t dwell dwell time at v wake before wake detection v wake = 200mv l 240 ns t ready startup time after wake detection l 10 s t idle idle timeout duration l 4.3 5.5 6.7 ms isospi pulse timing specifications (see figure 19) t 1/2pw (cs) chip-select half-pulse width l 120 150 180 ns t inv(cs) chip-select pulse inversion delay l 200 ns t 1/2pw (d) data half-pulse width l 40 50 60 ns t inv(d) data pulse inversion delay l 70 ns spi timing requirements (see figure 15 and figure 20) t clk sck period (note 4) l 1 s t 1 sdi setup time before sck rising edge l 25 ns t 2 sdi hold time after sck rising edge l 25 ns t 3 sck low t clk = t 3 + t 4 1s l 200 ns t 4 sck high t clk = t 3 + t 4 1s l 200 ns t 5 csb rising edge to csb falling edge l 0.65 s t 6 sck rising edge to csb rising edge (note 4) l 0.8 s t 7 csb falling edge to sck rising edge (note 4) l 1 s the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. the test conditions are v + = 39.6v, v reg = 5.0v unless otherwise noted.
ltc 6804 -1/ ltc 6804 -2 9 680412f for more information www.linear.com/LTC6804-1 electrical characteristics symbol parameter conditions min typ max units isospi timing specifications (see figure 19) t 8 sck falling edge to sdo valid (note 5) l 60 ns t 9 sck rising edge to short 1 transmit l 50 ns t 10 csb transition to long 1 transmit l 60 ns t 11 csb rising edge to sdo rising (note 5) l 200 ns t rtn data return delay l 430 525 ns t dsy(cs) chip-select daisy-chain delay l 150 200 ns t dsy(d) data daisy-chain delay l 300 360 ns t lag data daisy-chain lag (vs chip- select) l 0 35 70 ns t 6(gov) data to chip-select pulse governor l 0.8 1.05 s the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. the test conditions are v + = 39.6v, v reg = 5.0v unless otherwise noted. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the adc specifications are guaranteed by the total measurement error specification. note 3: the active state current is calculated from dc measurements. the active state current is the additional average supply current into v reg when there is continuous 1mhz communications on the isospi ports with 50% data 1s and 50% data 0s. slower clock rates reduce the supply current. see applications information section for additional details. note 4: these timing specifications are dependent on the delay through the cable, and include allowances for 50ns of delay each direction. 50ns corresponds to 10m of cat -5 cable (which has a velocity of propagation of 66% the speed of light). use of longer cables would require derating these specs by the amount of additional delay. note 5: these specifications do not include rise or fall time of sdo. while fall time (typically 5ns due to the internal pull-down transistor) is not a concern, rising-edge transition time t rise is dependent on the pull-up resistance and load capacitance on the sdo pin. the time constant must be chosen such that sdo meets the setup time requirements of the mcu. note 6: v + needs to be greater than or equal to the highest c(n) voltage for accurate measurements. see the graph top cell measurement error vs v + .
ltc 6804 -1/ ltc 6804 -2 10 680412f for more information www.linear.com/LTC6804-1 measurement error vs input, normal mode measurement error vs input, filtered mode measurement error vs input, fast mode measurement error vs temperature measurement error due to ir reflow measurement error long- term drift typical performance characteristics measurement noise vs input, normal mode measurement noise vs input, filtered mode measurement noise vs input, fast mode t a = 25c, unless otherwise noted. temperature (c) ?50 measurement error (mv) 1.5 25 680412 g01 0 ?1.0 ?25 0 50 ?1.5 ?2.0 2.0 1.0 0.5 ?0.5 75 100 125 cell voltage = 3.3v 5 typical units change in gain error (ppm) ?125 number of parts 20 25 30 25 50 75 ?50 ?25 0 680412 g02 15 10 ?100 ?75 5 0 35 260c, 1 cycle time (hours) 0 measurement error (ppm) 30 5 25 15 20 10 0 680412 g03 3000 1000 2000 2500 500 1500 cell voltage = 3.3v 8 typical parts input (v) 0 measurement error (mv) ?0.5 0 0.5 3 5 680412 g04 ?1.0 ?1.5 ?2.0 1 2 4 1.0 1.5 2.0 10 adc measurements averaged at each input input (v) 0 measurement error (mv) ?0.5 0 0.5 3 5 680412 g05 ?1.0 ?1.5 ?2.0 1 2 4 1.0 1.5 2.0 input (v) 0 measurement error (mv) 2 6 10 4 680412 g06 ?2 ?6 0 4 8 ?4 ?8 ?10 1 2 3 5 10 adc measurements averaged at each input input (v) 0 peak noise (mv) 0.6 0.8 1.0 4 680412 g07 0.4 0.2 0.5 0.7 0.9 0.3 0.1 0 1 2 3 5 input (v) 0 peak noise (mv) 0.6 0.8 1.0 4 680412 g08 0.4 0.2 0.5 0.7 0.9 0.3 0.1 0 1 2 3 5 input (v) 0 peak noise (mv) 6 8 10 4 680412 g09 4 2 5 7 9 3 1 0 1 2 3
ltc 6804 -1/ ltc 6804 -2 11 680412f for more information www.linear.com/LTC6804-1 typical performance characteristics measurement gain error hysteresis, hot measurement gain error hysteresis, cold noise filter response measurement error vs v reg measurement error v + psrr vs frequency measurement error v reg psrr vs frequency t a = 25c, unless otherwise noted. change in gain error (ppm) ?50 number of parts 15 20 25 t a = 85c to 25c ?20 0 30 680412 g10 10 5 0 ?40 ?30 ?10 10 20 change in gain error (ppm) ?40 0 number of parts 5 10 15 20 ?20 0 20 40 680412 g11 25 30 t a = ?45c to 25c ?30 ?10 10 30 input frequency (hz) 10 noise rejection (db) 0 ?50 ?10 ?30 ?20 ?40 ?70 ?60 680412 g12 1m 1k 100k 100 10k filtered 2khz 3khz adc mode: normal 15khz fast v reg (v) 4.5 measurement error (mv) 0 0.5 1.0 5.3 5.4 680412 g13 ?0.5 ?1.0 ?2.0 4.7 4.9 5.1 4.6 5.5 4.8 5.0 5.2 ?1.5 2.0 1.5 v in = 2v v in = 3.3v v in = 4.2v frequency (hz) 100 psrr (db) ?60 ?50 ?40 1m 680412 g14 ?70 ?80 ?65 ?55 ?45 ?75 ?85 ?90 1k 10k 100k 10m v + dc = 39.6v v + ac = 5v p-p 1 bit change < ?90db v reg generated from drive pin, figure 28 frequency (hz) 100 ?20 ?10 0 1m 68412 g15 ?30 ?40 1k 10k 100k 10m ?50 ?60 ?70 psrr (db) v reg(dc) = 5v v reg(ac) = 500mv p-p 1 bit change < ?70db cell measurement error vs input rc values gpio measurement error vs input rc values top cell measurement error vs v + input resistor, r () 1 cell measurement error (mv) 0 5 10 10000 680412 g16 ?5 ?10 ?20 10 100 1000 ?15 20 normal mode conversions differential rc filter on every c pin. expect cell-to-cell and part-to-part variations in error if r > 100 and/or c > 10nf 15 c = 0 c = 10nf c = 100nf c = 1f input resistance, r () 1 measurement error (mv) 2 6 10 10000 680412 g17 ?2 ?6 0 4 8 ?4 ?8 ?10 10 100 1000 100000 c = 0 c = 100nf c = 1f c = 10f time between measurements > 3rc v + (v) 36 ?1.0 cell 12 measurement error (mv) ?0.8 ?0.4 ?0.2 0 1.0 0.4 38 40 680412 g18 ?0.6 0.6 0.8 0.2 42 44 c12-c11 = 3.3v c12 = 39.6v
ltc 6804 -1/ ltc 6804 -2 12 680412f for more information www.linear.com/LTC6804-1 typical performance characteristics cell measurement error vs common mode voltage cell measurement cmrr vs frequency measurement error vs v + sleep supply current vs v + standby supply current vs v + refup supply current vs v + t a = 25c, unless otherwise noted. c11 voltage (v) 0 ?1.0 cell 12 measurement error (mv) ?0.8 ?0.4 ?0.2 0 1.0 0.4 10 20 680412 g19 ?0.6 0.6 0.8 0.2 30 c12-c11 = 3.3v v + = 39.6v frequency (hz) 100 ?90 rejection (db) ?80 ?60 ?50 ?40 10k 1m 10m 0 680412 g20 ?70 1k 100k ?30 ?20 ?10 v cm(in) = 5v p-p normal mode conversions v + (v) 5 measurement error (mv) 1.5 20 680412 g21 0 ?1.0 10 15 25 ?1.5 ?2.0 2.0 1.0 0.5 ?0.5 30 35 40 measurement error of cell 1 with 3.3v input. v reg generated from drive pin, figure 28 v + (v) 5 15 2 sleep supply current (a) 4 7 25 45 55 680412 g22 3 6 5 35 65 75 125c 85c 25c ?45c sleep supply current = v + current + v reg current v + (v) 155 40 standby supply current (a) 50 80 25 45 55 680412 g23 70 60 35 65 75 125c 85c 25c ?45c standby supply current = v + current + v reg current v + (v) 155 850 refup supply current (a) 1000 25 45 55 680412 g24 950 900 35 65 75 125c 85c 25c ?45c refup supply current = v + current + v reg current measure mode supply current vs v + measurement time vs temperature internal die temperature measurement error vs temperature v + (v) 5 measure mode supply current (ma) 12.00 12.25 12.50 35 55 680412 g25 11.75 11.50 15 25 45 65 75 11.25 11.00 125c 85c 25c ?45c measure mode supply current = v + current + v reg current temperature (c) ?50 measurement time (s) 2420 25 680412 g26 2360 2320 ?25 0 50 2300 2280 2440 2400 2380 2340 75 100 125 v reg = 5v v reg = 4.5v v reg = 5.5v 12 cell normal mode time shown. all adc measure times scale proportionally temperature (c) ?50 ?10 temperature measurement error (deg) ?8 ?4 ?2 0 10 4 0 50 75 100 680412 g27 ?6 6 8 2 ?25 25 125 5 typical units
ltc 6804 -1/ ltc 6804 -2 13 680412f for more information www.linear.com/LTC6804-1 typical performance characteristics v ref2 vs temperature v ref2 load regulation v ref2 v + line regulation v ref2 v reg line regulation v ref2 hysteresis, hot v ref2 power-up v ref2 hysteresis, cold v ref2 long- term drift v ref2 change due to ir reflow t a = 25c, unless otherwise noted. temperature (c) ?50 v ref2 (v) 3.001 3.002 3.003 25 75 680412 g28 3.000 2.999 ?25 0 50 100 125 2.998 2.997 v + = 39.6v 5 typical parts i out (ma) 0.01 change in v ref2 (ppm) ?600 ?400 680412 g29 ?800 ?1000 0.1 1 10 0 ?200 125c 85c 25c ?45c v + = 39.6v v reg = 5v v + (v) 5 change in v ref2 (ppm) 150 35 580412 g30 0 ?100 15 25 45 ?150 ?200 200 100 50 ?50 55 65 75 125c 85c 25c ?45c v reg generated from drive pin, figure 28 v reg (v) 4.5 ?150 change in v ref2 (ppm) ?100 ?50 0 50 100 150 r l = 5k 4.75 5 5.25 5.5 680412 g31 125c 85c 25c ?45c v ref2 (v) csb 1.5 2.5 3.5 680412 g32 0.5 5 1.0 2.0 3.0 0 0 ?5 1ms/div v ref2 csb r l = 5k c l = 1f time (hours) 0 change in v ref2 (ppm) 0 680412 g33 ?50 ?100 1000 2000 500 1500 2500 50 100 ?25 ?75 25 75 3000 8 typical parts change in ref2 (ppm) ?125 number of parts 15 20 25 t a = 85c to 25c 75 680412 g34 10 5 0 ?75 ?25 25 125 175 change in ref2 (ppm) ?250 number of parts 8 12 680412 g35 4 0 ?200 ?150 ?100 ?50 0 50 100 16 6 10 2 14 t a = ?45c to 25c change in ref2 (ppm) 0 number of parts 10 20 30 260c, 1 cycle 5 15 25 ?500 ?300 ?100 100 680412 g36 300 ?700
ltc 6804 -1/ ltc 6804 -2 14 680412f for more information www.linear.com/LTC6804-1 typical performance characteristics drive and v reg pin power-up v ref1 power-up v ref1 vs temperature internal die temperature increase vs discharge current isospi current (ready) vs temperature isospi current (ready/active) vs isospi clock frequency discharge switch on-resistance vs cell voltage drive pin load regulation drive pin line regulation t a = 25c, unless otherwise noted. cell voltage (v) 0 discharge switch on-resistance () 5 15 20 25 50 35 1 2 680412 g37 10 40 45 30 3 4 5 125c 85c 25c ?45c on-resistance of internal discharge switch measured with 100. external discharge resistor between s(n) and c(n) i load (ma) 0.01 change in drive pin voltage (mv) ?60 ?40 1 680412 g38 ?80 ?100 0.1 0 ?20 125c 85c 25c ?45c v + = 39.6v v + (v) 5 15 ?15 change in drive pin voltage (mv) ?5 10 25 45 55 680412 g39 ?10 5 0 35 65 75 125c 85c 25c ?45c 4 5 6 680412 g40 3 2 100s/div 1 0 ?1 v drive and v reg (v) v drive v reg v reg : c l = 1f v reg generated from drive pin, figure 28 v ref1 (v) csb 1.5 2.5 3.5 680412 g41 0.5 5 ?5 1.0 2.0 3.0 csb 0 1ms/div v ref1 c l = 1f temperature (c) ?50 3.145 v ref1 (v) 3.146 3.148 3.149 3.150 3.155 3.152 0 50 75 100 680412 g42 3.147 3.153 3.154 3.151 ?25 25 125 5 typical internal discharge current (ma per cell) 0 0 increase in die temperature (c) 5 15 20 25 50 35 20 40 680412 g43 10 40 45 30 60 80 12 cells discharging 1 cell discharging 6 cells discharging isospi clock frequency (khz) 0 10 12 14 800 680412 g45 8 6 200 400 600 1000 4 2 0 isospi current (ma) write read LTC6804-1 ltc6804-2 isomd = v reg i b = 1ma temperature (c) ?50 ?25 4 isospi current (ma) 6 9 0 50 75 680412 g44 5 8 7 25 100 125 i b = 1ma lt6804-1 isomd = v reg lt6804-2 isomd = v reg lt6804-1, isomd = 0
ltc 6804 -1/ ltc 6804 -2 15 680412f for more information www.linear.com/LTC6804-1 typical performance characteristics isospi driver current gain (port a/portb) vs temperature isospi driver common mode voltage (port a/port b) vs pulse amplitude isospi comparator threshold gain (port a/port b) vs common mode isospi comparator threshold gain (port a/port b) vs icmp voltage typical wake-up pulse amplitude (port a) vs dwell time i bias voltage vs temperature i bias voltage load regulation isospi driver current gain (port a/portb) vs bias current t a = 25c, unless otherwise noted. temperature (c) ?50 1.98 ibias pin voltage (v) 1.99 2.00 2.01 2.02 ?25 0 25 50 680412 g46 75 100 125 i b = 1ma 3 parts bias current (a) 0 ibias pin voltage (v) 2.000 2.005 800 408912 g47 1.995 1.990 200 400 600 1000 2.010 bias current (a) 0 current gain (ma/ma) 21 22 23 800 680412 g48 20 19 18 200 400 600 1000 v a = 0.5v v a = 1.0v v a = 1.6v temperature (c) ?50 ?25 18 current gain (ma/ma) 20 23 0 50 75 680412 g49 19 22 21 25 100 125 i b = 100a i b = 1ma pulse amplitude (v) 0 2.5 driver common mode (v) 3.0 3.5 4.0 4.5 5.0 5.5 0.5 1.0 1.5 2.0 i b = 100a i b = 1ma 680412 g50 common mode voltage (v) 2.5 0.44 comparator threshold gain (v/v) 0.46 0.48 0.50 0.52 0.56 3.0 3.5 4.0 4.5 680412 g51 5.0 5.5 0.54 v icmp = 1v v icmp = 0.2v icmp voltage (v) 0 0.44 comparator threshold gain (v/v) 0.46 0.48 0.50 0.52 0.4 0.8 1.2 1.6 680412 g52 0.54 0.56 0.2 0.6 1.0 1.4 3 parts wake-up dwell time, t dwell (ns) 0 wake-up pulse amplitude, v wake (mv) 150 200 600 680412 g53 100 50 150 300 450 300 250 guaranteed wake-up region
ltc 6804 -1/ ltc 6804 -2 16 680412f for more information www.linear.com/LTC6804-1 typical performance characteristics t a = 25c, unless otherwise noted. write command to a daisy-chained device (isomd = 0) data read-back from a daisy-chained device (isomd = 0) write command to a daisy-chained device (isomd = 1) data read-back from a daisy-chained device (isomd = 1) csb 5v/div sdi 5v/div sck 5v/div sdo 5v/div ipb-imb 2v/div (port b) 1s/div 680412 g54 isomd = v ? beginning of a command port a ipb-imb 1v/div (port b) ipa-ima 1v/div (port a) 1s/div 680412 g55 isomd = v reg beginning of a command csb 5v/div sdi 5v/div sck 5v/div sdo 5v/div ipb-imb 2v/div (port b) port a 1s/div 680412 g56 isomd = v ? end of a read command ipb-imb 1v/div (port b) ipa-ima 1v/div (port a) 1s/div 680412 g57 isomd = v reg end of a read command
ltc 6804 -1/ ltc 6804 -2 17 680412f for more information www.linear.com/LTC6804-1 pin functions c0 to c12: cell inputs. s1 to s12: balance inputs/outputs . 12 n- mosfets are connected between s(n) and c(n C 1) for discharging cells. v + : positive supply pin. v C : negative supply pins. the v C pins must be shorted together, external to the ic. v ref2 : buffered 2nd reference voltage for driving multiple 10k thermistors. bypass with an external 1f capacitor. v ref1 : adc reference voltage . bypass with an external 1f capacitor. no dc loads allowed. gpio[1:5]: general purpose i/o. can be used as digital inputs or digital outputs, or as analog inputs with a mea- surement range from v C to 5v. gpio [3:5] can be used as an i 2 c or spi port. swten : software timer enable. connect this pin to v reg to enable the software timer. drive: connect the base of an npn to this pin. connect the collector to v + and the emitter to v reg . v reg : 5v regulator input. bypass with an external 1f capacitor. isomd: serial interface mode. connecting isomd to v reg configures pins 41 to 44 of the ltc6804 for 2-wire isolated interface (isospi) mode. connecting isomd to v C configures the ltc6804 for 4-wire spi mode. wdt: watchdog timer output pin. this is an open drain nmos digital output. it can be left unconnected or con- nected with a 1m resistor to v reg . if the ltc6804 does not receive a valid command within 2 seconds, the watchdog timer circuit will reset the ltc6804 and the wdt pin will go high impedance. serial port pins LTC6804-1 (daisy-chainable) ltc6804-2 (addressable) isomd = v reg isomd = v C isomd = v reg isomd = v C port b ( pins 45 to 48) ipb ipb a3 a3 imb imb a2 a2 icmp icmp a1 a1 ibias ibias a0 a0 port a ( pins 41 to 44) (nc) sdo ibias sdo (nc) sdi icmp sdi ipa sck ipa sck ima csb ima csb csb, sck, sdi, sdo: 4-wire serial peripheral interface (spi). active low chip select (csb), serial clock (sck ), and serial data in (sdi) are digital inputs. serial data out (sdo) is an open drain nmos output pin. sdo requires a 5k pull-up resistor. a0 to a3: address pins. these digital inputs are connected to v reg or v C to set the chip address for addressable se- rial commands. ipa , ima: isolated 2-wire serial interface port a. ipa (plus) and ima (minus) are a differential input/output pair. ipb, imb: isolated 2-wire serial interface port b. ipb (plus) and imb (minus) are a differential input/output pair. ibias : isolated interface current bias . tie ibias to v C through a resistor divider to set the interface output current level. when the isospi interface is enabled, the ibias pin voltage is 2v. the ipa /ima or ipb/imb output current drive is set to 20 times the current, i b , sourced from the ibias pin. icmp: isolated interface comparator voltage threshold set. tie this pin to the resistor divider between ibias and v C to set the voltage threshold of the isospi receiver comparators. the comparator thresholds are set to 1/2 the voltage on the icmp pin.
ltc 6804 -1/ ltc 6804 -2 18 680412f for more information www.linear.com/LTC6804-1 block diagram c12 c11 c10 c9 c8 c7 c0 c6 c5 c4 c3 c2 c1 ? + 680412 bd1 ipb p imb icmp ibias sdo/(nc) sdi/(nc) sck/(ipa) csb/(ima) isomd wdt drive v reg swten v ref1 v ref2 gpio5 gpio4 v ? v ? * gpio3 gpio2 gpio1 c0 s1 v + c12 s12 c11 m s11 c10 s10 c9 s9 c8 s8 c7 s7 c6 s6 c5 s5 c4 s4 c3 s3 c2 s2 c1 logic and memory digital filters serial i/o port b 6-cell mux v regd soc v reg p m aux mux 12 balance fets s(n) c(n ? 1) p m 6-cell mux por v regd v reg serial i/o port a software timer die temperature 2nd reference 1st reference regulators adc2 ? + adc1 16 16 v + ldo1 v regd por v + ldo2 drive 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 LTC6804-1
ltc 6804 -1/ ltc 6804 -2 19 680412f for more information www.linear.com/LTC6804-1 block diagram sdo/(ibias) c12 c11 c10 c9 c8 c7 c0 c6 c5 c4 c3 c2 c1 ? + 680412 bd2 a4 p a3 a2 a1 sdi/(icmp) sck/(ipa) csb/(ima) isomd wdt drive swten gpio5 gpio4 gpio3 gpio2 gpio1 c0 s1 c12 s12 c11 m s11 c10 s10 c9 s9 c8 s8 c7 s7 c6 s6 c5 s5 c4 s4 c3 s3 c2 s2 c1 logic and memory digital filters serial i/o address 6-cell mux v regd soc v reg p m aux mux p m 6-cell mux por v regd v reg serial i/o port a software timer die temperature 2nd reference 1st reference regulators adc2 ? + adc1 v + ldo1 v regd por v + ldo2 drive v reg v ref1 v ref2 v ? v ? * v + 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 16 16 12 balance fets s(n) c(n ? 1) ltc6804-2
ltc 6804 -1/ ltc 6804 -2 20 680412f for more information www.linear.com/LTC6804-1 operation state diagram the operation of the ltc6804 is divided into two separate sections: the core circuit and the isospi circuit . both sec- tions have an independent set of operating states, as well as a shutdown timeout. ltc6804 core state descriptions sleep state the reference and adcs are powered down. the watchdog timer (see watchdog and software discharge timer ) has timed out. the software discharge timer is either disabled or timed out. the supply currents are reduced to minimum levels. the isospi ports will be in the idle state. if a wakeup signal is received (see waking up the serial interface ), the ltc6804 will enter the standby state. standby state the reference and the adcs are off . the watchdog timer and / or the software discharge timer is running. the drive pin powers the v reg pin to 5v through an external transistor. ( alternatively , v reg can be powered by an external supply ). when a valid adc command is received or the refon bit is set to 1 in the configuration register group, the ic pauses for t refup to allow for the reference to power up and then enters either the refup or measure state. otherwise , after t sleep (when both the watchdog and software dis- charge timer have expired) the ltc6804 returns to the figure 1. ltc6804 operation state diagram sleep state. if the software discharge timer is disabled, only the watchdog timer is relevant. refup state to reach this state the refon bit in the configuration reg- ister group must be set to 1 (using the wrcfg command, see table 36). the adcs are off. the reference is powered up so that the ltc6804 can initiate adc conversions more quickly than from the standby state. when a valid adc command is received, the ic goes to the measure state to begin the conversion. otherwise , the ltc 6804 will return to the standby state when the refon bit is set to 0, either manually (using wrcfg command) or automatically when the watchdog timer expires. (the ltc6804 will then move straight into the sleep state if both timers are expired). measure state the ltc6804 performs adc conversions in this state. the reference and adcs are powered up. after adc conversions are complete the ltc6804 will transition to either the refup or standby states, de- pending on the refon bit. additional adc conversions can be initiated more quickly by setting refon = 1 to take advantage of the refup state. note : non-adc commands do not cause a core state tran- sition. only an adc conversion or diagnostic commands will place the core in the measure state. 680412 f01 isospi port core ltc6804 conversion done (refon = 1) wakeup signal (t wake ) adc command (t refup ) adc command refon = 1 (t refup ) wakeup signal (core = standby) (t ready ) wakeup signal (core = sleep) (t wake ) transmit/receive note: state transition delays denoted by (t x ) no activity on isospi port idle timeout (t idle ) conversion done (refon = 0) refon = 0 wd timeout or swt timeout (t sleep ) measure refup standby sleep active ready idle
ltc 6804 -1/ ltc 6804 -2 21 680412f for more information www.linear.com/LTC6804-1 operation isospi state descriptions note: the LTC6804-1 has two isospi ports (a and b), for daisy-chain communication. the ltc6804-2 has only one isospi port (a), for parallel-addressable communication. idle state the isospi ports are powered down. when isospi port a receives a wakeup signal (see wak - ing up the serial interface ), the isospi enters the ready state. this transition happens quickly (within t ready ) if the core is in the standby state because the drive and v reg pins are already biased up. if the core is in the sleep state when the isospi receives a wakeup signal, then it transitions to the ready state within t wake . ready state the isospi port(s) are ready for communication. port b is enabled only for LTC6804-1, and is not present on the ltc6804-2. the serial interface current in this state depends on if the part is LTC6804-1 or ltc6804-2, the status of the isomd pin, and r bias = r b1 + r b2 (the external resistors tied to the ibias pin). if there is no activity (i.e., no wakeup signal) on port a for greater than t idle = 5.5ms, the ltc6804 goes to the idle state. when the serial interface is transmitting or receiving data the ltc6804 goes to the active state. active state the ltc6804 is transmitting/receiving data using one or both of the isospi ports. the serial interface consumes maximum power in this state . the supply current increases with clock frequency as the density of isospi pulses increases. power consumption the ltc6804 is powered via two pins: v + and v reg . the v + input requires voltage greater than or equal to the top cell voltage, and it provides power to the high voltage elements of the core circuitry . v + can be directly connected to the top cell of the battery stack, or to an external supply. the v reg input requires 5v and provides power to the remain- ing core circuitry and the isospi circuitry . the v reg input can be powered through an external transistor, driven by the regulated drive output pin. alternatively, v reg can be powered by an external supply. the power consumption varies according to the opera- tional states. table 1 and table 2 provide equations to approximate the supply pin currents in each state. the v + pin current depends only on the core state and not on the isospi state. however, the v reg pin current depends on both the core state and isospi state, and can therefore be divided into two components. the isospi interface draws current only from the v reg pin. i reg = i reg(core) + i reg(isospi) table 1. core supply current state i v + i reg(core) sleep v reg = 0v 3.8a 0a v reg = 5v 1.6a 2.2a standby 32a 35a refup 550a 450a measure 550a 11.5ma in the sleep state the v reg pin will draw approximately 2.2a if powered by a external supply. otherwise , the v + pin will supply the necessary current. adc operation there are two adcs inside the ltc6804. the two adcs operate simultaneously when measuring twelve cells. only one adc is used to measure the general purpose inputs. the following discussion uses the term adc to refer to one or both adcs, depending on the operation being performed . the following discussion will refer to adc1 and adc2 when it is necessary to distinguish between the two circuits, in timing diagrams, for example. adc modes the adcopt bit (cfgr0[0]) in the configuration register group and the mode selection bits md[1:0] in the conver - sion command together provide 6 modes of operation for the adc which correspond to different over sampling ratios (osr). the accuracy of these modes are summarized in table 3. in each mode, the adc first measures the inputs, and then performs a calibration of each channel. the names of the modes are based on the C3db bandwidth of the adc measurement.
ltc 6804 -1/ ltc 6804 -2 22 680412f for more information www.linear.com/LTC6804-1 table 2. isospi supply current equations isospi state device isomd connection i reg(isospi) idle LTC6804-1/ltc6804-2 n/a 0ma ready LTC6804-1 v reg 2.8ma + 5 ? i b v C 1.6ma + 3 ? i b ltc6804-2 v reg 1.8ma + 3 ? i b v C 0ma active LTC6804-1 v reg write: 2.8ma + 5 ? i b + 2 ? i b + 0.4ma ( ) ? 1s t clk read: 2.8ma + 5 ? i b + 3 ? i b + 0.5ma ( ) ? 1s t clk v C 1.6ma + 3 ? i b + 2 ? i b + 0.2ma ( ) ? 1s t clk ltc6804-2 v reg write: 1.8ma + 3 ? i b + 0.3ma ( ) ? 1s t clk read: 1.8ma + 3 ? i b + i b + 0.3ma ( ) ? 1s t clk v C 0ma operation mode 7khz (normal): in this mode, the adc has high resolution and low tme (total measurement error). this is considered the normal operating mode because of the optimum combination of speed and accuracy. mode 27khz (fast): in this mode, the adc has maximum throughput but has some increase in tme (total measurement error). so this mode is also referred to as the fast mode. the increase in speed comes from a reduction in the oversampling ratio. this results in an increase in noise and average measurement error. mode 26hz (filtered): in this mode, the adc digital filter C3db frequency is lowered to 26hz by increasing the osr. this mode is also referred to as the filtered mode due to its low C3db frequency. the accuracy is similar to the 7khz (normal) mode with lower noise. modes 14khz, 3khz and 2khz: modes 14 khz , 3 khz and 2 khz provide additional options to set the adc digital filter C3 db frequency at 13.5 khz , 3.4 khz and 1.7khz respectively. the accuracy of the 14khz mode is similar to the 27khz (fast) mode. the accuracy of 3khz and 2khz modes is similar to the 7khz (normal) mode. table 3. adc filter bandwidth and accuracy mode C3db filter bw C40db filter bw tme spec at 3.3v, 25c tme spec at 3.3v,C40c, 85c 27khz (fast mode) 27khz 84khz 4.7mv 4.7mv 14khz 13.5khz 42khz 4.7mv 4.7mv 7khz (normal mode) 6.8khz 21khz 1.2mv 2.2mv 3khz 3.4khz 10.5khz 1.2mv 2.2mv 2khz 1.7khz 5.3khz 1.2mv 2.2mv 26hz (filtered mode) 26hz 82hz 1.2mv 2.2mv note: tme is the total measurement error.
ltc 6804 -1/ ltc 6804 -2 23 680412f for more information www.linear.com/LTC6804-1 operation the conversion times for these modes are provided in table 5. if the core is in standby state, an additional t refup time is required to power up the reference before beginning the adc conversions. the reference can remain powered up between adc conversions if the refon bit in configuration register group is set to 1 so the core is in refup state after a delay t refup . then , the subsequent adc commands will not have the t refup delay before beginning adc conversions. adc range and resolution the c inputs and gpio inputs have the same range and resolution . the adc inside the ltc 6804 has an approximate range from C0.82 v to 5.73 v . negative readings are rounded to 0v. the format of the data is a 16-bit unsigned integer where the lsb represents 100v. therefore, a reading of 0 x 80 e 8 (33,000 decimal ) indicates a measurement of 3.3 v . delta - sigma adcs have quantization noise which depends on the input voltage, especially at low over sampling ratios (osr), such as in fast mode. in some of the adc modes, the quantization noise increases as the input voltage ap- proaches the upper and lower limits of the adc range. for example, the total measurement noise versus input voltage in normal and filtered modes is shown in figure 2. the specified range of the adc is 0v to 5v. in table 4, the precision range of the adc is arbitrarily defined as 0.5v to 4.5v. this is the range where the quantization noise is relatively constant even in the lower osr modes (see figure 2). table 4 summarizes the total noise in this range for all six adc operating modes. also shown is the noise free resolution. for example , 14-bit noise free resolution in normal mode implies that the top 14 bits will be noise free with a dc input, but that the 15th and 16th least significant bits (lsb) will flicker. adc range vs voltage reference value: typical delta-sigma adcs have a range which is exactly twice the value of the voltage reference, and the adc measurement error is directly proportional to the error in the voltage reference. the ltc6804 adc is not typi- cal. the absolute value of v ref1 is trimmed up or down to compensate for gain errors in the adc. therefore, the adc total measurement error (tme) specifications are superior to the v ref1 specifications. for example, the 25c specification of the total measurement error when measuring 3.300v in 7khz (normal) mode is 1.2mv and the 25c specification for v ref1 is 3.200v 100mv. table 4. adc range and resolution mode full range 1 specified range precision range 2 lsb format max noise noise free resolution 3 27khz (fast) C0.8192v to 5.7344v 0v to 5v 0.5v to 4.5v 100v unsigned 16 bits 4mv p-p 10 bits 14khz 1mv p-p 12 bits 7khz (normal) 250v p-p 14 bits 3khz 150v p-p 14 bits 2khz 100v p-p 15 bits 26hz (filtered) 50v p-p 16 bits 1. negative readings are rounded to 0v. 2. precision range is the range over which the noise is less than max noise. 3. noise free resolution is a measure of the noise level within the precision range. figure 2. measurement noise vs input voltage adc input voltage (v) 0 0.5 peak noise (mv) 1.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0 4.03.53.02.52.0 1.0 1.5 4.5 680412 f02 5.0 normal mode filtered mode
ltc 6804 -1/ ltc 6804 -2 24 680412f for more information www.linear.com/LTC6804-1 measuring cell voltages (adcv command) the adcv command initiates the measurement of the battery cell inputs, pins c0 through c12. this command has options to select the number of channels to measure and the adc mode. see the section on commands for the adcv command format. figure 3 illustrates the timing of adcv command which measures all twelve cells. after the receipt of the adcv command to measure all 12 cells, adc1 sequentially measures the bottom 6 cells. adc2 sequentially measures the top 6 cells. after the cell measurements are complete, each channel is calibrated to remove any offset errors. table 5 shows the conversion times for the adcv com- mand measuring all 12 cells. the total conversion time is given by t 6c which indicates the end of the calibration step. figure 4 illustrates the timing of the adcv command that measures only two cells. table 6 shows the conversion time for adcv command measuring only 2 cells. t 1c indicates the total conversion time for this command. operation figure 3. timing for adcv command measuring all 12 cells table 6. conversion times for adcv command measuring only 2 cells in different modes conversion times (in s) mode t 0 t 1m t 1c 27khz 0 57 201 14khz 0 86 230 7khz 0 144 405 3khz 0 240 501 2khz 0 493 754 26hz 0 29,817 33,568 table 5. conversion times for adcv command measuring all 12 cells in different modes conversion times (in s) mode t 0 t 1m t 2m t 5m t 6m t 1c t 2c t 5c t 6c 27khz 0 57 103 243 290 432 568 975 1,113 14khz 0 86 162 389 465 606 742 1,149 1,288 7khz 0 144 278 680 814 1,072 1,324 2,080 2,335 3khz 0 260 511 1,262 1,512 1,770 2,022 2,778 3,033 2khz 0 493 976 2,425 2,908 3,166 3,418 4,175 4,430 26hz 0 29,817 59,623 149,043 178,850 182,599 186,342 197,571 201,317 calibrate c8 to c7 calibrate c7 to c6 measure c12 to c11 measure c8 to c7 measure c7 to c6 adc2 serial interface t cycle t skew2 adcv + pec calibrate c2 to c1 calibrate c12 to c11 calibrate c6 to c5 calibrate c1 to c0 measure c6 to c5 measure c2 to c1 measure c1 to c0 adc1 t 0 t 1m t 2m t 6m t 5m t 1c t 2c t 5c t 6c 680412 f03 t refup figure 4. timing for adcv command measuring 2 cells calibrate c10 to c9 measure c10 to c9 adc2 serial interface adcv + pec calibrate c4 to c3 measure c4 to c3 adc1 t 0 t 1m t 1c 680412 f04 t refup
ltc 6804 -1/ ltc 6804 -2 25 680412f for more information www.linear.com/LTC6804-1 operation table 7. conversion times for adax command measuring all gpios and 2nd reference in different modes conversion times (in s) mode t 0 t 1m t 2m t 5m t 6m t 1c t 2c t 5c t 6c 27khz 0 57 103 243 290 432 568 975 1,113 14khz 0 86 162 389 465 606 742 1,149 1,288 7khz 0 144 278 680 814 1,072 1,324 2,080 2,335 3khz 0 260 511 1,262 1,512 1,770 2,022 2,778 3,033 2khz 0 493 976 2,425 2,908 3,166 3,418 4,175 4,430 26hz 0 29,817 59,623 149,043 178,850 182,599 186,342 197,571 201,317 figure 5. timing for adax command measuring all gpios and 2nd reference adc2 serial interface t cycle t skew adax + pec calibrate gpio2 calibrate 2nd ref calibrate gpio1 measure 2nd ref measure gpio2 measure gpio1 adc1 t 0 t 1m t 2m t 6m t 5m t 1c t 2c t 5c t 6c 680412 f05 t refup under/ overvoltage monitoring whenever the c inputs are measured, the results are com- pared to undervoltage and overvoltage thresholds stored in memory . if the reading of a cell is above the overvoltage limit, a bit in memory is set as a flag. similarly, measure- ment results below the undervoltage limit cause a flag to be set. the overvoltage and undervoltage thresholds are stored in the configuration register group . the flags are stored in the status register group b. auxiliary (gpio) measurements (adax command) the adax command initiates the measurement of the gpio inputs. this command has options to select which gpio input to measure (gpio1-5) and which adc mode. the adax command also measures the 2nd reference. there are options in the adax command to measure each gpio and the 2nd reference separately or to measure all 5 gpios and the 2nd reference in a single command. see the section on commands for the adax command format. all auxiliary measurements are relative to the v C pin voltage. this command can be used to read external temperature by connecting the temperature sensors to the gpios. these sensors can be powered from the 2nd reference which is also measured by the adax command, resulting in precise ratiometric measurements. figure 5 illustrates the timing of the adax command measuring all gpios and the 2nd reference. since all the 6 measurements are carried out on adc1 alone, the conversion time for the adax command is similar to the adcv command. measuring cell voltages and gpios ( adcvax command) the adcvax command combines twelve cell measure- ments with two gpio measurements (gpio1 and gpio2). this command simplifies the synchronization of battery cell voltage and current measurements when current sen- sors are connected to gpio1 or gpio2 inputs. figure ?6 illustrates the timing of the adcvax command. see the section on commands for the adcvax command format. the synchronization of the current and voltage measure- ments, t skew1 , in fast mode is within 208s.
ltc 6804 -1/ ltc 6804 -2 26 680412f for more information www.linear.com/LTC6804-1 operation calibrate measure c12 to c11 measure c11 to c10 measure c10 to c9 measure c9 to c8 measure c8 to c7 measure c7 to c6 adc2 serial interface t cycle t skew1 t skew1 adcvax + pec calibrate measure c6 to c5 measure c5 to c4 measure c4 to c3 measure gpio2 measure gpio1 measure c3 to c2 measure c2 to c1 measure c1 to c0 adc1 t 0 t 1m t 2m t 3m t 4m t 5m t 6m t 7m t 8m t 8c t refup 680412 f06 figure 6. timing of adcvax command table 8 shows the conversion and synchronization time for the adcvax command in different modes. the total conversion time for the command is given by t 8c . d ata acquisition system diagnostics the battery monitoring data acquisition system is com- prised of the multiplexers, adcs, 1st reference, digital filters, and memory. to ensure long term reliable perfor - mance there are several diagnostic commands which can be used to verify the proper operation of these circuits. measuring internal device parameters ( adstat command) the adstat command is a diagnostic command that measures the following internal device parameters: sum of all cells (soc), internal die temperature (itmp), analog power supply (va ) and the digital power supply (vd). these parameters are described in the section below. all 6 adc modes are available for these conversions. see the section on commands for the adstat command format. figure 7 illustrates the timing of the adstat command measuring all 4 internal device parameters. table 8. conversion and synchronization times for adcvax command in different modes conversion times (in s) synchronization time (s) mode t 0 t 1m t 2m t 3m t 4m t 5m t 6m t 7m t 8m t 8c t skew1 27khz 0 57 106 155 216 265 326 375 424 1,564 208 14khz 0 86 161 237 320 396 479 555 630 1,736 310 7khz 0 144 278 412 553 687 828 962 1,096 3,133 543 3khz 0 260 511 761 1,018 1,269 1,526 1,777 2,027 4,064 1009 2khz 0 493 976 1,459 1,949 2,432 2,923 3,406 3,888 5,925 1939 26 hz 0 29,817 59,623 89,430 119,244 149,051 178,864 208,671 238,478 268,442 119234 figure 7. timing for adstat command measuring soc, itmp, va , vd adc2 serial interface t cycle t skew adstat + pec calibrate itmp calibrate vd calibrate soc measure vd measure itmp measure soc adc1 t 0 t 1m t 2m t 4m t 3m t 1c t 2c t 3c t 4c 680412 f07 t refup
ltc 6804 -1/ ltc 6804 -2 27 680412f for more information www.linear.com/LTC6804-1 operation table 9. conversion times for adstat command measuring soc, itmp, va , vd conversion times (in s) mode t 0 t 1m t 2m t 3m t 4m t 1c t 2c t 3c t 4c 27khz 0 57 103 150 197 338 474 610 748 14khz 0 86 162 237 313 455 591 726 865 7khz 0 144 278 412 546 804 1,056 1,308 1,563 3khz 0 260 511 761 1,011 1,269 1,522 1,774 2,028 2khz 0 493 976 1,459 1,942 2,200 2,452 2,705 2,959 26hz 0 29,817 59,623 89,430 119,237 122,986 126,729 130,472 134,218 table 9 shows the conversion time of the adstat com- mand measuring all 4 internal parameters. t 4c indicates the total conversion time for the adstat command. sum of cells measurement: the sum of all cells measure- ment is the voltage between c12 and c0 with a 20:1 attenu- ation. the 16-bit adc value of sum of cells measurement (soc) is stored in status register group a. from the soc value , the sum of all cell voltage measurements is given by : sum of all cells = soc ? 20 ? 100v internal die temperature : the adstat command can measure the internal die temperature. the 16-bit adc value of the die temperature measurement (itmp) is stored in status register group a. from itmp the actual die temperature is calculated using the expression: internal die temperature ( c ) = ( itmp ) ? 100 v / (7.5mv)c C 273c power supply measurements: the adstat command is also used to measure the analog power supply (v reg ) and digital power supply (v regd ). the 16-bit adc value of the analog power supply measure- ment (va ) is stored in status register group a. the 16-bit adc value of the digital power supply measurement (vd) is stored in status register group b. from va and vd, the power supply measurements are given by: analog power supply measurement ( v reg ) = v a ? 100 v digital power supply measurement ( v regd ) = v d ? 100 v the nominal range of v reg is 4.5v to 5.5v. the nominal range of v regd is 2.7v to 3.6v. accuracy check measuring an independent voltage reference is the best means to verify the accuracy of a data acquisition system. the ltc6804 contains a 2nd reference for this purpose. the adax command will initiate the measurement of the 2nd reference. the results are placed in auxiliary register group b. the range of the result depends on the adc measurement accuracy and the accuracy of the 2nd ref- erence, including thermal hysteresis and long term drift. readings outside the range 2.980 to 3.020 indicate the system is out of its specified tolerance. mux decoder check the diagnostic command diagn ensures the proper operation of each multiplexer channel. the command cycles through all channels and sets the muxfail bit to 1 in status register group b if any channel decoder fails. the muxfail bit is set to 0 if the channel decoder passes the test. the muxfail bit is also set to 1 on power-up (por) or after a clrstat command. the diagn command takes about 400s to complete if the core is in refup state and about 4.5ms to complete if the core is in standby state. the polling methods described in the section polling methods can be used to determine the completion of the diagn command. digital filter check the delta-sigma adc is composed of a 1-bit pulse den- sity modulator followed by a digital filter. a pulse density modulated bit stream has a higher percentage of 1s for higher analog input voltages. the digital filter converts this high frequency 1-bit stream into a single 16-bit word.
ltc 6804 -1/ ltc 6804 -2 28 680412f for more information www.linear.com/LTC6804-1 operation this is why a delta-sigma adc is often referred to as an oversampling converter. the self test commands verify the operation of the digital filters and memory . figure 8 illustrates the operation of the adc during self test. the output of the 1-bit pulse density modulator is replaced by a 1-bit test signal. the test signal passes through the digital filter and is con- verted to a 16-bit value. the 1-bit test signal undergoes the same digital conversion as the regular 1-bit pulse from the modulator, so the conversion time for any self test command is exactly the same as the corresponding regular adc conversion command. the 16-bit adc value is stored in the same register groups as the regular adc conversion command. the test signals are designed to place alternating one-zero patterns in the registers. table 10 provides a list of the self test commands. if the digital filters and memory are working properly , then the registers will contain the values shown in table 10. for more details see the section commands. table 10. self test command summary command self test option output pattern in different adc modes results register groups 27khz 14khz 7khz 3khz 2khz 26hz cvst st[1:0]=01 0x9565 0x9553 0x9555 0x9555 0x9555 0x9555 c1v to c12v ( cva , cvb, cvc, cvd) st[1:0]=10 0x6a9a 0x6aac 0x6aaa 0x6aaa 0x6aaa 0x6aaa axst st[1:0]=01 0x9565 0x9553 0x9555 0x9555 0x9555 0x9555 g1 v to g5v, ref (auxa, auxb) st[1:0]=10 0x6a9a 0x6aac 0x6aaa 0x6aaa 0x6aaa 0x6aaa statst st[1:0]=01 0x9565 0x9553 0x9555 0x9555 0x9555 0x9555 soc, itmp, va , vd ( stata , statb ) st[1:0]=10 0x6a9a 0x6aac 0x6aaa 0x6aaa 0x6aaa 0x6aaa figure 8. operation of ltc6804 adc self test 680412 f08 results register digital filter analog input mux test signal pulse density modulated bit stream 1 self test pattern generator 16 1-bit modulator adc clear commands ltc6804 has 3 clear commands C clrcell, clraux and clrstat . these commands clear the registers that store all adc conversion results. the clrcell command clears cell voltage register group a, b, c and d. all bytes in these registers are set to 0xff by clrcell command. the clraux command clears auxiliary register group a and b. all bytes in these registers are set to 0xff by clraux command. the clrstat command clears status register group a and b except the revcode in status register group b. a read back of revcode will return the revision code of the part. rsvd bits always read back 0s. all ov flags, uv flags, muxfail bit, rsvd bits and thsd bit in status register group b are set to 1 by clrstat command. the thsd bit is set to 0 after rdstatb command. the regis- ters storing soc, itmp, va and vd are all set to 0xff by clrstat command.
ltc 6804 -1/ ltc 6804 -2 29 680412f for more information www.linear.com/LTC6804-1 operation open-wire check (adow command) the adow command is used to check for any open wires between the adcs in the ltc6804 and the external cells. this command performs adc conversions on the c pin inputs identically to the adcv command, except two internal current sources sink or source current into the two c pins while they are being measured. the pull-up (pup) bit of the adow command determines whether the current sources are sinking or sourcing 100a. the following simple algorithm can be used to check for an open wire on any of the 13 c pins (see figure 9): 1) run the 12-cell command adow with pup = 1 at least twice. read the cell voltages for cells 1 through 12 once at the end and store them in array cell pu(n) . 2) run the 12-cell command adow with pup = 0 at least twice. read the cell voltages for cells 1 through 12 once at the end and store them in array cell pd(n) . 3) take the difference between the pull-up and pull-down measurements made in above steps for cells 2-12: cell ?(n) = cell pu(n) C cell pd(n) . 4) for all values of n from 1 to 11: if cell ?(n+1) < C400 mv, then c(n) is open. if the cell pu(1) = 0.0000, then c(0) is open. if the cell pd(12) = 0.0000, then c(12) is open. the above algorithm detects open wires using normal mode conversions with as much as 10nf of capacitance remaining on the ltc6804 side of the open wire. however, if more external capacitance is on the open c pin, then the length of time that the open wire conversions are ran in steps 1 and 2 must be increased to give the 100a current sources time to create a large enough difference for the algorithm to detect an open connection. this can be accomplished by running more than two adow commands in steps 1 and 2, or by using filtered mode conversions instead of normal mode conversions. use table 11 to determine how many conversions are necessary: table 11 number of adow commands required in steps 1 and 2 external c pin capacitance normal mode filtered mode 10nf 2 2 100nf 10 2 1f 100 2 c 1+roundup(c/10nf) 2 thermal shutdown to protect the ltc6804 from overheating , there is a thermal shutdown circuit included inside the ic. if the temperature detected on the die goes above approximately 150 c, the thermal shutdown circuit trips and resets the configura- tion register group to its default state. this turns off all discharge switches. when a thermal shutdown event has occurred, the thsd bit in status register group b will go high. this bit is cleared after a read operation has been performed on the status register group b ( rdstatb command). the clrstat command sets the thsd bit 2 + + + + + + + v + v ? 100a 100a pup = 1 c12 pup = 0 v + v + v ? adc2 ltc6804 4 c11 6 c10 8 c9 6-cell mux 10 c8 12 14 c7 c6 c6 1 16 + + + + + v + v ? 100a 100a pup = 1 c5 pup = 0 v + v ? v ? 680412 f09 adc1 18 c4 20 c3 22 c2 6-cell mux 24 c1 26 30 31 c0 figure 9. open-wire detection circuitry
ltc 6804 -1/ ltc 6804 -2 30 680412f for more information www.linear.com/LTC6804-1 operation high for diagnostic purposes, but does not reset the configuration register group. revision code the status register group b contains a 4-bit revision code. if software detection of device revision is necessary , then contact the factory for details. otherwise , the code can be ignored. in all cases, however, the values of all bits must be used when calculating the packet error code (pec) on data reads . watchdog and software discharge timer when there is no valid command for more than 2 seconds, the watchdog timer expires. this resets configuration reg- ister bytes cfgr0-cfgr3 in all cases. cfgr4 and cfgr5 are reset by the watchdog timer when the software timer is disabled . the wdt pin is pulled high by the external pull - up when the watchdog time elapses. the watchdog timer is always enabled and it resets after every valid command. the software discharge timer is used to keep the discharge switches turned on for programmable time duration. if the software timer is being used, the discharge switches are not turned off when the watchdog timer is activated. to enable the software timer, swten pin needs to be tied high to v reg (figure 10). the discharge switches can now be kept on for the programmed time duration that is de- termined by the dcto value written to the configuration register. table 12 shows the various time settings and the corresponding dcto value. table 13 summarizes the status of the configuration register group after a watchdog timer or software timer event. table 13 watchdog timer software timer swten = 0, dcto = xxxx resets cfgr0-5 when it activates disabled swten = 1, dcto = 0000 resets cfgr0-5 when it activates disabled swten = 1, dcto ! = 0000 resets cfgr0-3 when it activates resets cfgr4-5 when it fires unlike the watchdog timer, the software timer does not reset when there is a valid command. the software timer can only be reset after a valid wrcfg (write configuration register) command. there is a possibility that the software timer will expire in the middle of some commands. if software timer activates in the middle of wrcfg com- mand, the configuration register resets as per table 14. table 12. dcto settings dcto 0 1 2 3 4 5 6 7 8 9 a b c d e f time min disabled 0.5 1 2 3 4 5 10 15 20 30 40 60 75 90 120 figure 10. watchdog and software discharge timer 680412 f10 v reg swten ltc6804 dcto > 0 2 sw timer timeout dcten en rst clk 1 rst (por or wrcfg done or timeout) (por or valid command) clk osc 16hz osc 16hz wdt wdtpd wdtrst && ~dcten rst1 (resets dcto, dcc) rst2 (resets refup, vuv, vov) wdtrst watchdog timer
ltc 6804 -1/ ltc 6804 -2 31 680412f for more information www.linear.com/LTC6804-1 operation table 15. comm register memory map register rd/wr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 comm0 rd/wr icom0[3] icom0[2] icom0[1] icom0[0] d0[7] d0[6] d0[5] d0[4] comm1 rd/wr d0[3] d0[2] d0[1] d0[0] fcom0[3] fcom0[2] fcom0[1] fcom0[0] comm2 rd/wr icom1[3] icom1[2] icom1[1] icom1[0] d1[7] d1[6] d1[5] d1[4] comm3 rd/wr d1[3] d1[2] d1[1] d1[0] fcom1[3] fcom1[2] fcom1[1] fcom1[0] comm4 rd/wr icom2[3] icom2[2] icom2[1] icom2[0] d2[7] d2[6] d2[5] d2[4] comm5 rd/wr d2[3] d2[2] d2[1] d2[0] fcom2[3] fcom2[2] fcom2[1] fcom2[0] however, at the end of the valid wrcfg command, the new data is copied to the configuration register. the new data is not lost when the software timer is activated. if software timer activates in the middle of rdcfg com- mand, the configuration register group resets as per table ?14. as a result, the read back data from bytes crfg4 and crfg5 could be corrupted. i 2 c/spi master on ltc6804 using gpios the i/o ports gpio3, gpio4 and gpio5 on LTC6804-1 and ltc6804-2 can be used as an i 2 c or spi master port to communicate to an i 2 c or spi slave. in the case of an i 2 c master, gpio4 and gpio5 form the sda and scl ports of the i 2 c interface respectively. in the case of a table 14 dcto (read value) time left (min) 0 disabled (or) timer has timed out 1 0 < timer 0.5 2 0.5 < timer 1 3 1 < timer 2 4 2 < timer 3 5 3 < timer 4 6 4 < timer 5 7 5 < timer 10 8 10 < timer 15 9 15 < timer 20 a 20 < timer 30 b 30 < timer 40 c 40 < timer 60 d 60 < timer 75 e 75 < timer 90 f 90 < timer 120 spi master, gpio3, gpio5 and gpio4 become the chip select (csbm), clock (sckm) and data (sdiom) ports of the spi interface respectively. the gpios are open drain outputs, so an external pull-up is required on these ports to operate as an i 2 c or spi master. it is also important to write the gpio bits to 1 in the cfg register group so these ports are not pulled low internally by the device. comm register ltc 6804 has a 6- byte comm register as shown in table ?15. this register stores all data and control bits required for i 2 c or spi communication to a slave. the comm register contains 3 bytes of data dn[7:0] to be transmitted to or received from the slave device. icomn [3:0] specify con- trol actions before transmitting/receiving the data byte. fcomn [3:0] specify control actions after transmitting/ receiving the data byte. if the bit icomn[3] in the comm register is set to 1 the part becomes an i 2 c master and if the bit is set to 0 the part becomes a spi master. table 16 describes the valid write codes for icomn[3:0] and fcomn[3:0] and their behavior when using the part as an i 2 c master. table 17 describes the valid codes for icomn[3:0] and fcomn[3:0] and their behavior when using the part as a spi master. note that only the codes listed in tables 16 and 17 are valid for icomn[3:0] and fcomn[3:0]. writing any other code that is not listed in tables 16 and 17 to icomn[3:0] and fcomn[3:0] may result in unexpected behavior on the i 2 c and spi ports.
ltc 6804 -1/ ltc 6804 -2 32 680412f for more information www.linear.com/LTC6804-1 operation table 17. write codes for icomn[3:0] and fcomn[3:0] on spi master control bits code action description icomn[3:0] 1000 csbm low generates a csbm low signal on spi port (gpio3) 1001 csbm high generates a csbm high signal on spi port (gpio3) 1111 no transmit releases the spi port and ignores the rest of the data fcomn[3:0] x000 csbm low holds csbm low at the end of byte transmission 1001 csbm high transitions csbm high at the end of byte transmission table 16. write codes for icomn[3:0] and fcomn[3:0] on i 2 c master control bits code action description icomn[3:0] 0110 start generate a start signal on i 2 c port followed by data transmission 0001 stop generate a stop signal on i 2 c port 0000 blank proceed directly to data transmission on i 2 c port 0111 no transmit release sda and scl and ignore the rest of the data fcomn[3:0] 0000 master ack master generates an ack signal on ninth clock cycle 1000 master nack master generates a nack signal on ninth clock cycle 1001 master nack + stop master generates a nack signal followed by stop signal comm commands three commands help accomplish i 2 c or spi communica- tion to the slave device: wrcomm, stcomm, rdcomm wrcomm command: this command is used to write data to the comm register. this command writes 6 bytes of data to the comm register. the pec needs to be written at the end of the data. if the pec does not match, all data in the comm register is cleared to 1s when csb goes high. see the section bus protocols for more details on a write command format. stcomm command: this command initiates i 2 c / spi com- munication on the gpio ports . the comm register contains 3 bytes of data to be transmitted to the slave. during this command, the data bytes stored in the comm register are transmitted to the slave i 2 c or spi device and the data received from the i 2 c or spi device is stored in the comm register. this command uses gpio4 (sda) and gpio5 (scl) for i 2 c communication or gpio3 (csbm), gpio4 (sdiom) and gpio5 (sckm) for spi communication. the stcomm command is to be followed by 24 clock cycles for each byte of data to be transmitted to the slave device while holding csb low. for example, to transmit 3 bytes of data to the slave, send stcomm command and its pec followed by 72 clock cycles. pull csb high at the end of the 72 clock cycles of stcomm command. during i 2 c or spi communication, the data received from the slave device is updated in the comm register. rdcomm command: the data received from the slave device can be read back from the comm register using the rdcomm command. the command reads back 6 bytes of data followed by the pec. see the section bus protocols for more details on a read command format. table 18 describes the possible read back codes for icomn [3:0] and fcomn [3:0] when using the part as an i 2 c master. dn[3:0] contains the data byte either transmitted by the i 2 c master or received from the i 2 c slave. in case of the spi master, the read back codes for icomn[3:0] and fcomn[3:0] are always 0111 and 1111 respectively. dn[3:0] contains the data byte either trans- mitted by the spi master or received from the spi slave. figure 11 illustrates the operation of ltc6804 as an i 2 c or spi master using the gpios. any number of bytes can be transmitted to the slave in groups of 3 bytes using these commands. the gpio ports will not get reset between different stcomm commands. however , if the wait time between the commands is greater than 2 seconds, the watchdog will timeout and reset the ports to their default values.
ltc 6804 -1/ ltc 6804 -2 33 680412f for more information www.linear.com/LTC6804-1 table 18. read codes for icomn[3:0] and fcomn[3:0] on i 2 c master control bits code description icomn[3:0] 0110 master generated a start signal 0001 master generated a stop signal 0000 blank, sda was held low between bytes 0111 blank, sda was held high between bytes fcomn[3:0] 0000 master generated an ack signal 0111 slave generated an ack signal 1111 slave generated a nack signal 0001 slave generated an ack signal, master generated a stop signal 1001 slave generated a nack signal, master generated a stop signal figure 11. ltc6804 i 2 c/spi master using gpios 680412 f11 comm register gpio port i 2 c/spi slave port a rdcomm wrcomm stcomm LTC6804-1/ltc6804-2 operation to transmit several bytes of data using an i 2 c master, a start signal is only required at the beginning of the entire data stream. a stop signal is only required at the end of the data stream. all intermediate data groups can use a blank code before the data byte and an ack/nack signal as appropriate after the data byte. sda and scl will not get reset between different stcomm commands. to transmit several bytes of data using spi master, a csbm low signal is sent at the beginning of the 1st data byte. csbm can be held low or taken high for intermediate data groups using the appropriate code on fcomn[3:0]. a csbm high signal is sent at the end of the last byte of data. csbm, sdiom and sckm will not get reset between different stcomm commands. figure 12 shows the 24 clock cycles following stcomm command for an i 2 c master in different cases. note that if icomn[3:0] specified a stop condition, after the stop signal is sent, the sda and scl lines are held high and all data in the rest of the word is ignored. if icomn[3:0] is a no transmit, both sda and scl lines are released, and rest of the data in the word is ignored. this is used when a particular device in the stack does not have to communicate to a slave. figure 12. stcomm timing diagram for an i 2 c master sda (gpio4) 680412 f12 scl (gpio5) no transmit sda (gpio4) scl (gpio5) stop sda (gpio4) scl (gpio5) start ack sda (gpio4) scl (gpio5) start nack + stop sda (gpio4) scl (gpio5) blank nack (sck) t clk t 4 t 3
ltc 6804 -1/ ltc 6804 -2 34 680412f for more information www.linear.com/LTC6804-1 operation figure 13. stcomm timing diagram for a spi master sdiom (gpio4) 680412 f13 sckm (gpio5) csbm high/no transmit csbm (gpio3) sdiom (gpio4) sckm (gpio5) csbm (gpio3) csbm low csbm low high sdiom (gpio4) sckm (gpio5) csbm (gpio3) csbm high low csbm low (sck) t clk t 4 t 3 figure 13 shows the 24 clock cycles following stcomm command for a spi master. similar to the i 2 c master, if icomn[3:0] specified a csbm high or a no transmit condition, the csbm, sckm and sdiom lines of the spi master are released and the rest of the data in the word is ignored. table 19. i 2 c master timing i 2 c master parameter timing relationship to primary spi interface timing specifications at t clk = 1s scl clock frequency 1/(2 ? t clk ) max 500khz t hd ; sta t 3 min 200ns t low t clk min 1s t high t clk min 1s t su ; sta t clk + t 4 * min 1.03s t hd ; dat t 4 * min 30ns t su ; dat t 3 min 1s t su ; sto t clk + t 4 * min 1.03s t buf 3 ? t clk min 3s *note: when using isospi , t 4 is generated internally and is a minimum of 30ns. also, t 3 = t clk C t 4 . when using spi, t 3 and t 4 are the low and high times of the sck input, each with a specified minimum of 200ns. table 20. spi master timing spi master parameter timing relationship to primary spi interface timing specifications at t clk = 1s sdiom valid to sckm rising setup t 3 min 200ns sdiom valid from sckm rising hold t clk + t 4 * min 1.03s sckm low t clk min 1s sckm high t clk min 1s sckm period (sckm_low + sckm_high) 2 ? t clk min 2s csbm pulse width 3 ? t clk min 3s sckm rising to csbm rising 5 ? t clk + t 4 * min 5.03 s csbm falling to sckm falling t 3 min 200ns csbm falling to sckm rising t clk + t 3 min 1.2s sckm falling to sdiom valid master requires < t clk *note: when using isospi, t 4 is generated internally and is a minimum of 30ns. also, t 3 = t clk C t 4 . when using spi, t 3 and t 4 are the low and high times of the sck input, each with a specified minimum of 200ns. timing specifications of i 2 c and spi master the timing of the ltc6804 i 2 c or spi master will be controlled by the timing of the communication at the ltc6804s primary spi interface . table 19 shows the i 2 c master timing relationship to the primary spi clock. table ?20 shows the spi master timing specifications.
ltc 6804 -1/ ltc 6804 -2 35 680412f for more information www.linear.com/LTC6804-1 figure 14. 4-wire spi configuration daisy-chain support 680412 f14 v + c12 s12 c11 s11 c10 s10 c9 s9 c8 s8 c7 s7 c6 s6 c5 s5 c4 s4 c3 s3 c2 s2 c1 miso mosi clk cs v dd mpu ipb imb icmp ibias sdo (nc) sdi (nc) sck (ipa) csb (ima) isomd wdt drive v reg swten v ref1 v ref2 gpio5 gpio4 v ? v ? gpio3 gpio2 gpio1 c0 s1 LTC6804-1 address pins 5k 5k v + c12 s12 c11 s11 c10 s10 c9 s9 c8 s8 c7 s7 c6 s6 c5 s5 c4 s4 c3 s3 c2 s2 c1 miso mosi clk cs v dd mpu a3 a2 a1 a0 sdo (ibias) sdi (icmp) sck (ipa) csb (ima) isomd wdt drive v reg swten v ref1 v ref2 gpio5 gpio4 v ? v ? gpio3 gpio2 gpio1 c0 s1 ltc6804-2 operation serial interface overview there are two types of serial ports on the ltc6804, a standard 4-wire serial peripheral interface ( spi) and a 2-wire isolated interface ( isospi). pins 41 through 44 are configurable as 2-wire or 4-wire serial port, based on the state of the isomd pin. there are two versions of the ltc6804: the LTC6804-1 and the ltc6804-2. the LTC6804-1 is used in a daisy chain configuration, and the ltc6804-2 is used in an addressable bus configuration. the LTC6804-1 provides a second isospi interface using pins 45 through 48. the ltc6804-2 uses pins 45 through 48 to set the address of the device, by tying these pins to v C or v reg . 4-wire serial peripheral interface (spi) physical layer external connections connecting isomd to v C configures serial port a for 4-wire spi. the sdo pin is an open drain output which requires a pull-up resistor tied to the appropriate supply voltage (figure?14). timing the 4-wire serial port is configured to operate in a spi system using cpha = 1 and cpol = 1. consequently, data on sdi must be stable during the rising edge of sck. the timing is depicted in figure 15. the maximum data rate is 1mbps.
ltc 6804 -1/ ltc 6804 -2 36 680412f for more information www.linear.com/LTC6804-1 operation figure 15. timing diagram of 4-wire serial peripheral interface figure 16. isospi interface 2-wire isolated interface (isospi) physical layer the 2-wire interface provides a means to interconnect ltc6804 devices using simple twisted pair cabling. the interface is designed for low packet error rates when the cabling is subjected to high rf fields. isolation is achieved through an external transformer. standard spi signals are encoded into differential pulses. the strength of the transmission pulse and the threshold level of the receiver are set by two external resistors. the values of the resistors allow the user to trade off power dissipation for noise immunity. figure 16 illustrates how the isospi circuit operates. a 2v reference drives the ibias pin. external resistors r b1 and r b2 create the reference current i b . this current sets the drive strength of the transmitter. r b1 and r b2 also form a voltage divider of the 2v reference at the icmp pin. this sets the threshold voltage of the receiver circuit. 680412 f15 sdi sck d3 d2 d1 d0 d7?d4 d3 current command previous command t 7 t 8 t 6 t 5 sdo csb d3 d4 d2 d1 d0 d7?d4 d3 t 1 t 2 t 3 t 4 680412 f16 ima or imb r m ibias v icmp /3 + 167mv i b r b1 icmp 2v ipa or ipb logic and memory tx = +1 tx ? 20 ? i b tx = ?1 sdo tx = 0 pulse encoder/ decoder sdi sck csb wakeup circuit (on port a) ltc6804 + ? + ? ? + ? ? rx = +1 rx = ?1 rx = 0 35k idle v reg idle 35k r b2 comparator threshold = ? v icmp 2 1 0.5x
ltc 6804 -1/ ltc 6804 -2 37 680412f for more information www.linear.com/LTC6804-1 operation external connections the LTC6804-1 has 2 serial ports which are called port b and port a . port b is always configured as a 2- wire interface (master). the final device in the daisy chain does not use this port, and it should be terminated into r m . port a is either a 2-wire or 4-wire interface (slave), depending on the connection of the isomd pin. figure 17 is an example of a robust interconnection of multiple identical pcbs, each containing one ltc6804 - 1. the microprocessor is located on a separate pcb. to achieve 2-wire isolation between the microprocessor pcb and the 1st LTC6804-1 pcb, use the ltc6820 support ic. the ltc6820 is functionally equivalent to the diagram in figure 16. the ltc6804-2 has a single serial port (port a) which can be 2-wire or 4-wire, depending on the state of the isomd pin. when configured for 2-wire communications, several devices can be connected in a multi-drop configuration, as shown in figure 18. the ltc6820 ic is used to interface the mpu (master) to the ltc6804-2s (slaves). selecting bias resistors the adjustable signal amplitude allows the system to trade power consumption for communication robustness, and the adjustable comparator threshold allows the system to account for signal losses. the isospi transmitter drive current and comparator volt- age threshold are set by a resistor divider (r bias = r b1 + r b2 ) between the ibias and v C . the divided voltage is connected to the icmp pin which sets the comparator threshold to 1/2 of this voltage (v icmp ). when either isospi interface is enabled (not idle) ibias is held at 2v, causing a current i b to flow out of the ibias pin. the ip and im pin drive currents are 20 ? i b . as an example, if divider resistor r b1 is 2.8k and resistor r b2 is 1.21k (so that r bias = 4k), then: i b = 2v r b1 + r b2 = 0.5ma i drv = i ip = i im = 20 ? i b = 10ma v icmp = 2v ? r b2 r b1 + r b2 = i b ? r b2 = 603mv v tcmp = 0.5 ? v icmp = 302mv in this example, the pulse drive current i drv will be 10ma, and the receiver comparators will detect pulses with ip-im amplitudes greater than 302mv. if the isolation barrier uses 1:1 transformers connected by a twisted pair and terminated with 120 resistors on each end, then the transmitted differential signal amplitude () will be: v a = i drv ? r m 2 = 0.6v (this result ignores transformer and cable losses, which may reduce the amplitude). isospi pulse detail tw o ltc6804 devices can communicate by transmitting and receiving differential pulses back and forth through an isolation barrier. the transmitter can output three voltage levels: +v a , 0v, and Cv a . a positive output results from ip sourcing current and im sinking current across load resistor r m . a negative voltage is developed by ip sink- ing and im sourcing . when both outputs are off, the load resistance forces the differential output to 0v.
ltc 6804 -1/ ltc 6804 -2 38 680412f for more information www.linear.com/LTC6804-1 operation 680412 f18 v + c12 s12 c11 s11 c10 s10 c9 s9 c8 s8 c7 s7 c6 s6 c5 s5 c4 s4 c3 s3 c2 s2 c1 a3 a2 a1 a0 sdo (ibias) sdi (icmp) sck (ipa) csb (ima) isomd wdt drive v reg swten v ref1 v ref2 gpio5 gpio4 v ? v ? gpio3 gpio2 gpio1 c0 s1 ltc6804-2 address = 0x0 v + c12 s12 c11 s11 c10 s10 c9 s9 c8 s8 c7 s7 c6 s6 c5 s5 c4 s4 c3 s3 c2 s2 c1 a3 a2 a1 a0 sdo (ibias) sdi (icmp) sck (ipa) csb (ima) isomd wdt drive v reg swten v ref1 v ref2 gpio5 gpio4 v ? v ? gpio3 gpio2 gpio1 c0 s1 ltc6804-2 address = 0x1 v + c12 s12 c11 s11 c10 s10 c9 s9 c8 s8 c7 s7 c6 s6 c5 s5 c4 s4 c3 s3 c2 s2 c1 a3 a2 a1 a0 sdo (ibias) sdi (icmp) sck (ipa) csb (ima) isomd wdt drive v reg swten v ref1 v ref2 gpio5 gpio4 v ? v ? gpio3 gpio2 gpio1 c0 s1 ltc6804-2 address = 0x2 v + c12 s12 c11 s11 c10 s10 c9 s9 c8 s8 c7 s7 c6 s6 c5 s5 c4 s4 c3 s3 c2 s2 c1 a3 a2 a1 a0 sdo (ibias) sdi (icmp) sck (ipa) csb (ima) isomd wdt drive v reg swten v ref1 v ref2 gpio5 gpio4 v ? v ? gpio3 gpio2 gpio1 c0 s1 ltc6804-2 address = 0x3 ? ? ? ? ? ? ? ? vdds en miso mosi sck cs vdd pol pha mstr icmp ibias gnd slow ip im miso mosi clk cs v dd mpu ltc6820 ? ? 680412 f17 vdds en miso mosi sck cs vdd pol pha mstr icmp ibias gnd slow ip im miso mosi clk cs v dd mpu ltc6820 v + c12 s12 c11 s11 c10 s10 c9 s9 c8 s8 c7 s7 c6 s6 c5 s5 c4 s4 c3 s3 c2 s2 c1 ipb imb icmp ibias sdo (nc) sdi (nc) sck (ipa) csb (ima) isomd wdt drive v reg swten v ref1 v ref2 gpio5 gpio4 v ? v ? gpio3 gpio2 gpio1 c0 s1 LTC6804-1 v + c12 s12 c11 s11 c10 s10 c9 s9 c8 s8 c7 s7 c6 s6 c5 s5 c4 s4 c3 s3 c2 s2 c1 ipb imb icmp ibias sdo (nc) sdi (nc) sck (ipa) csb (ima) isomd wdt drive v reg swten v ref1 v ref2 gpio5 gpio4 v ? v ? gpio3 gpio2 gpio1 c0 s1 LTC6804-1 v + c12 s12 c11 s11 c10 s10 c9 s9 c8 s8 c7 s7 c6 s6 c5 s5 c4 s4 c3 s3 c2 s2 c1 ipb imb icmp ibias sdo (nc) sdi (nc) sck (ipa) csb (ima) isomd wdt drive v reg swten v ref1 v ref2 gpio5 gpio4 v ? v ? gpio3 gpio2 gpio1 c0 s1 LTC6804-1 v + c12 s12 c11 s11 c10 s10 c9 s9 c8 s8 c7 s7 c6 s6 c5 s5 c4 s4 c3 s3 c2 s2 c1 ipb imb icmp ibias sdo (nc) sdi (nc) sck (ipa) csb (ima) isomd wdt drive v reg swten v ref1 v ref2 gpio5 gpio4 v ? v ? gpio3 gpio2 gpio1 c0 s1 LTC6804-1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? figure 18. multi-drop configuration using ltc6804-2 figure 17. transformer-isolated daisy-chain configuration using LTC6804-1
ltc 6804 -1/ ltc 6804 -2 39 680412f for more information www.linear.com/LTC6804-1 operation to eliminate the dc signal component and enhance reli- ability, the isospi uses two different pulse lengths. this allows for four types of pulses to be transmitted, as shown in table 21. a +1 pulse will be transmitted as a positive pulse followed by a negative pulse. a C1 pulse will be transmitted as a negative pulse followed by a positive pulse. the duration of each pulse is defined as t 1/2pw , since each is half of the required symmetric pair. (the total isospi pulse duration is 2 ? t 1/2pw ). table 21. isospi pulse types pulse type first level (t 1/2pw ) second level (t 1/2pw ) ending level long +1 +v a (150ns) Cv a (150ns) 0v long C1 Cv a (150ns) +v a (150ns) 0v short +1 +v a (50ns) Cv a (50ns) 0v short C1 Cv a (50ns) +v a (50ns) 0v a host microcontroller does not have to generate isospi pulses to use this 2-wire interface . the first ltc6804 in the system can communicate to the microcontroller using the 4-wire spi interface on its port a, then daisy-chain to other ltc6804s using the 2-wire isospi interface on its port b. alternatively, an ltc6820 can be used to translate the spi signals into isospi pulses. LTC6804-1 operation with port a configured for spi when the LTC6804-1 is operating with port a as an spi (isomd = v C ), the spi detects one of four communication events: csb falling, csb rising, sck rising with sdi = 0, and sck rising with sdi = 1. each event is converted into one of the four pulse types for transmission through the LTC6804-1 daisy chain. long pulses are used to transmit csb changes and short pulses are used to transmit data, as explained in table 22. table 22. LTC6804-1 port b (master) isospi port function communication event ( port a spi) transmitted pulse ( port b isospi) csb rising long +1 csb falling long C1 sck rising edge, sdi = 1 short +1 sck rising edge, sdi = 0 short C1 on the other side of the isolation barrier (i.e. at the other end of the cable), the 2nd ltc6804 will have isomd = v reg . its port a operates as a slave isospi interface . it receives each transmitted pulse and reconstructs the spi signals internally, as shown in table 23. in addition, during a read command this port may transmit return data pulses. figure 19. isospi pulse detail +v tcmp +v a ?v tcmp v ip ? v im +1 pulse ?v a t 1/2pw t inv t 1/2pw +v tcmp +v a ?v tcmp v ip ? v im ?v a t 1/2pw t inv t 1/2pw 680412 f19 ?1 pulse
ltc 6804 -1/ ltc 6804 -2 40 680412f for more information www.linear.com/LTC6804-1 operation figure 20. isospi timing diagram table 23. LTC6804-1 port a (slave) isospi port function received pulse ( port a isospi) internal spi port action return pulse long +1 drive csb high none long C1 drive csb low short +1 1. set sdi = 1 2. pulse sck short C1 pulse if reading a 0 bit (no return pulse if not in read mode or if reading a 1 bit) short C1 1. set sdi = 0 2. pulse sck the lower isospi port (port a) never transmits long ( csb) pulses. furthermore, a slave isospi port will only transmit short C1 pulses, never a +1 pulse. the master port recognizes a null response as a logic 1. this allows for multiple slave devices on a single cable without risk of collisions (multidrop). figure 20 shows the isospi timing diagram for a read command to daisy-chained LTC6804-1 parts. the isomd pin is tied to v C on the bottom part so its port a is config- ured as a spi port (csb, sck, sdi and sdo). the isospi signals of three stacked devices are shown, labeled with the port (a or b) and part number. note that iso b1 and iso a2 is actually the same signal, but shown on each end of the transmission cable that connects parts 1 and 2. likewise, iso b2 and iso a3 is the same signal, but with the cable delay shown between parts 2 and 3. bits w n -w 0 refers to the 16-bit command code and the 16-bit pec of a read command. at the end of bit w 0 the 3 parts decode the read command and begin shifting out data which is valid on the next rising edge of clock sck. bits x n -x 0 refer to the data shifted out by part 1. bits y n -y 0 680412 f20 sdi sck sdo csb iso a2 iso b2 iso a3 iso b1 read data command 6000 5000 4000 3000 2000 1000 0 t 7 t 6 t 5 t rtn t 11 t 10 t 2 t 1 t clk t 4 t 3 t rise t dsy(cs) t 8 t 9 t dsy(cs) z n-1 z n-1 z n z n w 0 w 0 w n w n y n-1 y n-1 y n y n w 0 w 0 x n-1 x n z 0 w n w n t dsy(d) t 10
ltc 6804 -1/ ltc 6804 -2 41 680412f for more information www.linear.com/LTC6804-1 operation refer to the data shifted out by part 2 and bits z n -z 0 refer to the data shifted out by part 3. all this data is read back from the sdo port on part 1 in a daisy-chained fashion. waking up the serial interface the serial ports (spi or isospi) will enter the low power idle state if there is no activity on port a for a time of t idle . the wakeup circuit monitors activity on pins 41 and 42. if isomd = v C , port a is in spi mode. activity on the csb or sck pin will wake up the spi interface . if isomd = v reg , port a is in isospi mode. differential activity on ipa -imb wakes up the isospi interface . the ltc6804 will be ready to communicate when the isospi state changes to ready within t wake or t ready , depending on the core state (see figure 1 and state descriptions for details.) the LTC6804-1 sends a long +1 pulse on port b after it is ready to communicate. in a daisy-chained configuration, this pulse wakes up the next device in the stack which will, in turn, wake up the next device. if there are n devices in the stack, all the devices are powered up within the time n ? t wake or n ? t ready , depending on the core state. for large stacks, the time n ? t wake may be equal to or larger than t idle . in this case, after waiting longer than the time of n ? t wake , the host may send another dummy byte and wait for the time n ? t ready , in order to ensure that all devices are in the ready state. figure 21 illustrates the timing and the functionally equivalent circuit . common mode signals will not wake up the serial interface . the interface is designed to wake up after receiving a large signal single-ended pulse, or a low-amplitude symmetric pulse. the differential signal |sck( ipa ) C csb(ima)|, must be at least v wake = 200 mv for a minimum duration of t dwell = 240 ns to qualify as a wake up signal that powers up the serial interface. d ata link layer all data transfers on ltc6804 occur in byte groups. every byte consists of 8 bits. bytes are transferred with the most significant bit (msb) first. csb must remain low for the entire duration of a command sequence, including between a command byte and subsequent data. on a write command, data is latched in on the rising edge of csb. network layer packet error code the packet error code (pec) is a 15-bit cyclic redundancy check (crc) value calculated for all of the bits in a reg- ister group in the order they are passed, using the initial pec seed value of 000000000010000 and the following characteristic polynomial: x15 + x14 + x10 + x8 + x7 + x4 + x3 + 1. to calculate the 15-bit pec value, a simple procedure can be established: figure 21. wake-up detection and idle timer 680412 f21 csb or ima sck or ipa |sck(ipa) - csb(ima)| wake-up state rejects common mode noise wake-up csb or ima sck or ipa low power mode t idle > 4.5ms t ready < 10s t dwell = 240ns v wake = 200mv low power mode ok to communicate t dwell = 240ns delay retriggerable t idle = 5.5ms one-shot
ltc 6804 -1/ ltc 6804 -2 42 680412f for more information www.linear.com/LTC6804-1 operation 1. initialize the pec to 000000000010000 ( pec is a 15-bit register group) 2. for each bit din coming into the pec register group, set in0 = din xor pec [14] in3 = in0 xor pec [2] in4 = in0 xor pec [3] in7 = in0 xor pec [6] in8 = in0 xor pec [7] in10 = in0 xor pec [9] in14 = in0 xor pec [13] 3. update the 15-bit pec as follows pec [14] = in14, pec [13] = pec [12], pec [12] = pec [11], pec [11] = pec [10], pec [10] = in10, pec [9] = pec [8], pec [8] = in8, pec [7] = in7, pec [6] = pec [5], pec [5] = pec [4], pec [4] = in4, pec [3] = in3, pec [2] = pec [1], pec [1] = pec [0], pec [0] = in0 figure 22. 15-bit pec computation circuit 680412 f22 din i/p o/p i/p pec register bit x xor gate x 0 1 2 3 4 5 6 7 8 9 14 10 11 12 13 4. go back to step 2 until all the data is shifted. the final pec (16 bits) is the 15-bit value in the pec register with a 0 bit appended to its lsb figure 22 illustrates the algorithm described above. an example to calculate the pec for a 16-bit word (0x0001) is listed in table 24. the pec for 0x0001 is computed as 0x3d6e after stuffing a 0 bit at the lsb. for longer data streams, the pec is valid at the end of the last bit of data sent to the pec register. ltc6804 calculates pec for any command or data received and compares it with the pec following the command or data. the command or data is regarded as valid only if the pec matches. ltc6804 also attaches the calculated pec at the end of the data it shifts out. table 25 shows the format of pec while writing to or reading from ltc6804. while writing any command to ltc6804, the command bytes cmd0 and cmd1 (see table 32 and table 33) and the pec bytes pec0 and pec1 are sent on port a in the following order: cmd0, cmd1, pec0, pec1 after a broadcast write command to daisy - chained LTC6804-1 devices, data is sent to each device followed by the pec. for example, when writing the configuration register group to two daisy - chained devices ( primary device p, stacked device s), the data will be sent to the primary device on port a in the following order: cfgr 0(s ), , cfgr5(s ), pec0(s ), pec1(s ), cfgr 0(p ), , cfgr5(p), pec0(p), pec1(p) after a read command for daisy-chained devices, each device shifts out its data and the pec that it computed for its data on port a followed by the data received on port b. for example, when reading status register group b from
ltc 6804 -1/ ltc 6804 -2 43 680412f for more information www.linear.com/LTC6804-1 table 24. pec calculation for 0x0001 pec[14] 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 pec[13] 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 pec[12] 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 1 1 pec[11] 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 1 1 1 pec[10] 0 0 0 0 0 0 1 0 0 0 0 1 1 0 1 1 1 1 pec[9] 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 1 pec[8] 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 pec[7] 0 0 0 1 0 0 0 0 0 0 0 1 1 1 0 1 1 1 pec[6] 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 pec[5] 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 pec[4] 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 pec[3] 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 pec[2] 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 pec[1] 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 pec[0] 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 in14 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 in10 0 0 0 0 0 1 0 0 0 0 1 1 0 1 1 1 pec word in8 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 in7 0 0 1 0 0 0 0 0 0 0 1 1 1 0 1 1 in4 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 in3 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 in0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 din 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 clock cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 operation table 25. write/read pec format name rd/wr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pec0 rd/wr pec[14] pec[13] pec[12] pec[11] pec[10] pec[9] pec[8] pec[7] pec1 rd/wr pec[6] pec[5] pec[4] pec[3] pec[2] pec[1] pec[0] 0 two daisy-chained devices ( primary device p, stacked device s), the primary device sends out data on port a in the following order: stbr 0(p ), , stbr 5(p ), pec 0(p ), pec 1(p ), stbr 0(s ), , stbr5(s), pec0(s), pec1(s) broadcast commands a broadcast command is one to which all devices on the bus will respond, regardless of device address. this com- mand can be used with LTC6804-1 and ltc6804-2 parts. see bus protocols for broadcast command format. with broadcast commands all devices can be sent commands simultaneously.
ltc 6804 -1/ ltc 6804 -2 44 680412f for more information www.linear.com/LTC6804-1 operation in parallel configurations, this is useful for adc conver - sion and polling commands. it can also be used with write commands when all parts are being written with the same data. broadcast read commands should not be used in the parallel configuration. daisy - chained configurations only support broadcast commands. all devices in the chain receive the command bytes simultaneously. for example, to initiate adc con- versions in a stack of devices, a single adcv command is sent, and all devices will start conversions at the same time. for read and write commands, a single command is sent, and then the stacked devices effectively turn into a cascaded shift register, in which data is shifted through each device to the next device in the stack. see the serial programming examples section. figure 23. sdo polling after an adc conversion command figure 24. sdo polling using pladc command 680412 f23 sdi sck t cycle sdo csb msb(cmd) lsb(pec) bit 14(cmd) 680412 f24 sdi sck sdo csb msb(cmd) lsb(pec) conversion done bit 14(cmd) address commands an address command is one in which only the addressed device on the bus responds. address commands are used only with ltc6804-2 parts. see bus protocols for address command format. polling methods the simplest method to determine adc completion is for the controller to start an adc conversion and wait for the specified conversion time to pass before reading the results . polling is not supported with daisy-chain communication. in parallel configurations that communicate in spi mode (isomd pin tied low), there are two methods of poll- ing. the first method is to hold csb low after an adc
ltc 6804 -1/ ltc 6804 -2 45 680412f for more information www.linear.com/LTC6804-1 operation conversion command is sent. after entering a conversion command, the sdo line is driven low when the device is busy performing conversions (figure 23). sdo is pulled high when the device completes conversions. however, the sdo will also go back high when csb goes high even if the device has not completed the conversion. an ad- dressed device drives the sdo line based on its status alone . a problem with this method is that the controller is not free to do other serial communication while wait- ing for adc conversions to complete. the next method overcomes this limitation. the controller can send an adc start command, perform other tasks, and then send a poll adc converter status (pladc) command to determine the status of the adc conversions (figure 24). after entering the pladc command, sdo will go low if the device is busy performing conversions. sdo is pulled high at the end of conversions. however, the sdo will also go high when csbi goes high even if the device has not completed the conversion. see programming examples on how to use the pladc command with devices in parallel configuration . in parallel configurations that communicate in isospi mode , the low side port transmits a data pulse only in response to a master isospi pulse received by it. so, after enter - ing the command in either method of polling described above, isospi data pulses are sent to the part to update the conversion status. these pulses can be sent using ltc6820 by simply clocking its sck pin. in response to this pulse, the ltc6804 returns an isospi pulse if it is still busy performing conversions and does not return a pulse if it has completed conversions. if a csb high isospi pulse is sent to the ltc6804, it exits the polling command. bus protocols protocol format: the protocol formats for both broadcast and address commands are depicted in table 27 through table 31. table 26 is the key for reading the protocol diagrams. table 26. protocol key cmd0 first command byte (see tables 32 and 33) cmd1 second command byte (see tables 32 and 33) pec0 first pec byte (see table 25) pec1 second pec byte (see table 25) n number of bytes continuation of protocol master to slave slave to master command format: the formats for the broadcast and address commands are shown in table 32 and table 33 respectively. the 11-bit command code cc[10:0] is the same for a broadcast or an address command. a list of all the command codes is shown in table 34. a broadcast command has a value 0 for cmd0[7] through cmd0[3]. an address command has a value 1 for cmd0[7] followed by the 4-bit address of the device (a3, a2, a1, a0) in bits cmd0[6:3]. an addressed device will respond to an address command only if the physical address of the device on pins a3 to a0 match the address specified in the address command. the pec for broadcast and address commands must be computed on the entire 16-bit command (cmd0 and cmd1). commands table 34 lists all the commands and its options for both LTC6804-1 and ltc6804-2
ltc 6804 -1/ ltc 6804 -2 46 680412f for more information www.linear.com/LTC6804-1 operation table 27. broadcast/address poll command 8 8 8 8 cmd0 cmd1 pec0 pec1 poll data table 28. broadcast write command 8 8 8 8 8 8 8 8 8 8 cmd0 cmd1 pec0 pec1 data byte low data byte high pec0 pec1 shift byte 1 shift byte n table 29. address write command 8 8 8 8 8 8 8 8 cmd0 cmd1 pec0 pec1 data byte low data byte high pec0 pec1 table 30. broadcast read command 8 8 8 8 8 8 8 8 8 8 cmd0 cmd1 pec 0 pec1 data byte low data byte high pec0 pec1 shift byte 1 shift byte n table 31. address read command 8 8 8 8 8 8 8 8 cmd0 cmd1 pec0 pec1 data byte low data byte high pec0 pec1 table 32. broadcast command format name rd/wr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cmd0 wr 0 0 0 0 0 cc[10] cc[9] cc[8] cmd1 wr cc[7] cc[6] cc[5] cc[4] cc[3] cc[2] cc[1] cc[0] table 33. address command format name rd/wr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cmd0 wr 1 a3* a2* a1* a0* cc[10] cc[9] cc[8] cmd1 wr cc[7] cc[6] cc[5] cc[4] cc[3] cc[2] cc[1] cc[0] *ax is address bit x
ltc 6804 -1/ ltc 6804 -2 47 680412f for more information www.linear.com/LTC6804-1 operation table 34. command codes command description name cc[10:0] - command code 10 9 8 7 6 5 4 3 2 1 0 write configuration register group wrcfg 0 0 0 0 0 0 0 0 0 0 1 read configuration register group rdcfg 0 0 0 0 0 0 0 0 0 1 0 read cell voltage register group a rdcva 0 0 0 0 0 0 0 0 1 0 0 read cell voltage register group b rdcvb 0 0 0 0 0 0 0 0 1 1 0 read cell voltage register group c rdcvc 0 0 0 0 0 0 0 1 0 0 0 read cell voltage register group d rdcvd 0 0 0 0 0 0 0 1 0 1 0 read auxiliary register group a rdauxa 0 0 0 0 0 0 0 1 1 0 0 read auxiliary register group b rdauxb 0 0 0 0 0 0 0 1 1 1 0 read status register group a rdstata 0 0 0 0 0 0 1 0 0 0 0 read status register group b rdstatb 0 0 0 0 0 0 1 0 0 1 0 start cell voltage adc conversion and poll status adcv 0 1 md[1] md [0] 1 1 dcp 0 ch[2] ch[1] ch[0] start open wire adc con- version and poll status adow 0 1 md[1] md[0] pup 1 dcp 1 ch[2] ch[1] ch[0] start self- test cell voltage conversion and poll status cvst 0 1 md[1] md[0] st[1] st[0] 0 0 1 1 1 start gpios adc conversion and poll status adax 1 0 md[1] md[0] 1 1 0 0 chg [2] chg [1] chg [0] start self- test gpios conversion and poll status axst 1 0 md[1] md[0] st[1] st[0] 0 0 1 1 1 start status group adc conversion and poll status adstat 1 0 md[1] md[0] 1 1 0 1 chst [2] chst [1] chst [0] start self- test status group conversion and poll status statst 1 0 md[1] md[0] st[1] st[0] 0 1 1 1 1 start combined cell voltage and gpio1, gpio2 conversion and poll status adcvax 1 0 md[1] md[0] 1 1 dcp 1 1 1 1 clear cell voltage register group clrcell 1 1 1 0 0 0 1 0 0 0 1 clear auxiliary register group clraux 1 1 1 0 0 0 1 0 0 1 0 clear status register group clrstat 1 1 1 0 0 0 1 0 0 1 1 poll adc conversion status pladc 1 1 1 0 0 0 1 0 1 0 0 diagnose mux and poll status diagn 1 1 1 0 0 0 1 0 1 0 1 write comm register group wrcomm 1 1 1 0 0 1 0 0 0 0 1 read comm register group rdcomm 1 1 1 0 0 1 0 0 0 1 0 start i 2 c/spi communication stcomm 1 1 1 0 0 1 0 0 0 1 1
ltc 6804 -1/ ltc 6804 -2 48 680412f for more information www.linear.com/LTC6804-1 operation table 35. command bit descriptions name description values md[1:0] adc mode md adcopt (cfgr0[0]) = 0 adcopt (cfgr0[0]) = 1 01 27khz mode (fast) 14khz mode 10 7khz mode (normal) 3khz mode 11 26hz mode (filtered) 2khz mode dcp discharge permitted dcp 0 discharge not permitted 1 discharge permitted ch[2:0] cell selection for adc conversion total conversion time in the 6 adc modes ch 27khz 14khz 7khz 3khz 2khz 26hz 000 all cells 1.1ms 1.3ms 2.3ms 3.0ms 4.4ms 201ms 001 cell 1 and cell 7 201s 230s 405s 501s 754s 34ms 010 cell 2 and cell 8 011 cell 3 and cell 9 100 cell 4 and cell 10 101 cell 5 and cell 11 110 cell 6 and cell 12 pup pull-up/pull-down current for open-wire conversions pup 0 pull-down current 1 pull-up current st[1:0] self- test mode selection self- test conversion result st 27khz 14khz 7khz 3khz 2khz 26hz 01 self test 1 0x9565 0x9553 0x9555 0x9555 0x9555 0x9555 10 self test 2 0x6a9a 0x6aac 0x6aaa 0x6aaa 0x6aaa 0x6aaa chg[2:0] gpio selection for adc conversion total conversion time in the 6 adc modes chg 27khz 14khz 7khz 3khz 2khz 26hz 000 gpio 1-5, 2nd ref 1.1ms 1.3ms 2.3ms 3.0ms 4.4ms 201ms 001 gpio 1 201s 230s 405s 501s 754s 34ms 010 gpio 2 011 gpio 3 100 gpio 4 101 gpio 5 110 2nd reference chst[2:0]* status group selection total conversion time in the 6 adc modes chst 27khz 14khz 7khz 3khz 2khz 26hz 000 soc, itmp, va , vd 748s 865s 1.6ms 2.0ms 3.0ms 134ms 001 soc 201s 230s 405s 501s 754s 34ms 010 itmp 011 va 100 vd *note: valid options for chst in adstat command are 0-4. if chst is set to 5/6 in adstat command, the ltc6804 treats it like adax command with chg = 5/6.
ltc 6804 -1/ ltc 6804 -2 49 680412f for more information www.linear.com/LTC6804-1 operation table 36. configuration register group register rd/wr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cfgr0 rd/wr gpio5 gpio4 gpio3 gpio2 gpio1 refon swtrd adcopt cfgr1 rd/wr vuv[7] vuv[6] vuv[5] vuv[4] vuv[3] vuv[2] vuv[1] vuv[0] cfgr2 rd/wr vov[3] vov[2] vov[1] vov[0] vuv[11] vuv[10] vuv[9] vuv[8] cfgr3 rd/wr vov[11] vov[10] vov[9] vov[8] vov[7] vov[6] vov[5] vov[4] cfgr4 rd/wr dcc8 dcc7 dcc6 dcc5 dcc4 dcc3 dcc2 dcc1 cfgr5 rd/wr dcto[3] dcto[2] dcto[1] dcto[0] dcc12 dcc11 dcc10 dcc9 table 37. cell voltage register group a register rd/wr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cvar 0 rd c1v[7] c1v[6] c1v[5] c1v[4] c1v[3] c1v[2] c1v[1] c1v[0] cvar 1 rd c1v[15] c1v[14] c1v[13] c1v[12] c1v[11] c1v[10] c1v[9] c1v[8] cvar 2 rd c2v[7] c2v[6] c2v[5] c2 v[4] c2v[3] c2v[2] c2v[1] c2v[0] cvar 3 rd c2v[15] c2v[14] c2v[13] c2v[12] c2v[11] c2v[10] c2v[9] c2v[8] cvar 4 rd c3v[7] c3v[6] c3v[5] c3v[4] c3v[3] c3v[2] c3v[1] c3v[0] cvar 5 rd c3v[15] c3v[14] c3v[13] c3v[12] c3v[11] c3v[10] c3v[9] c3v[8] table 38. cell voltage register group b register rd/wr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cvbr0 rd c4v[7] c4v[6] c4v[5] c4v[4] c4v[3] c4v[2] c4v[1] c4v[0] cvbr1 rd c4v[15] c4v[14] c4v[13] c4v[12] c4v[11] c4v[10] c4v[9] c4v[8] cvbr2 rd c5v[7] c5v[6] c5v[5] c5v[4] c5v[3] c5v[2] c5v[1] c5v[0] cvbr3 rd c5v[15] c5 v[14] c5v[13] c5v[12] c5v[11] c5v[10] c5v[9] c5v[8] cvbr4 rd c6v[7] c6v[6] c6v[5] c6v[4] c6v[3] c6v[2] c6v[1] c6v[0] cvbr5 rd c6v[15] c6v[14] c6v[13] c6v[12] c6v[11] c6v[10] c6v[9] c6v[8] table 39. cell voltage register group c register rd/wr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cvcr0 rd c7v[7] c7v[6] c7v[5] c7v[4] c7v[3] c7v[2] c7v[1] c7v[0] cvcr1 rd c7v[15] c7v[14] c7v[13] c7v[12] c7v[11] c7v[10] c7v[9] c7v[8] cvcr2 rd c8v[7] c8v[6] c8v[5] c8v[4] c8v[3] c8v[2] c8v[1] c8v[0] cvcr3 rd c8v[15] c8v[14] c8v[13] c8v[12] c8v[11] c8v[10] c8v[9] c8v[8] cvcr 4 rd c9v[7] c9v[6] c9v[5] c9v[4] c9v[3] c9v[2] c9v[1] c9v[0] cvcr5 rd c9v[15] c9v[14] c9v[13] c9v[12] c9v[11] c9v[10] c9v[9] c9v[8] table 40. cell voltage register group d register rd/wr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cvdr0 rd c10v[7] c10v[6] c10v[5] c10v[4] c10v[3] c10v[2] c10v[1] c10v [0] cvdr1 rd c10v[15] c10v[14] c10v[13] c10v[12] c10v[11] c10v[10] c10v[9] c10v[8] cvdr2 rd c11v[7] c11v[6] c11v[5] c11v[4] c11v[3] c11v[2] c11v[1] c11v[0] cvdr3 rd c11v[15] c11v[14] c11v[13] c11v[12] c11v[11] c11v[10] c11v[9] c11v[8] cvdr4 rd c12v[7] c12v[6] c12v[5] c12v[4] c12v[3] c12v[2] c 12v[1] c12v[0] cvdr5 rd c12v[15] c12v[14] c12v[13] c12v[12] c12v[11] c12v[10] c12v[9] c12v[8]
ltc 6804 -1/ ltc 6804 -2 50 680412f for more information www.linear.com/LTC6804-1 table 41. auxiliary register group a register rd/wr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 avar 0 rd g1v[7] g1v[6] g1v[5] g1v[4] g1v[3] g1v[2] g1v[1] g1v[0] avar 1 rd g1v[15] g1v[14] g1v[13] g1v[12] g1v[11] g1v[10] g1v[9] g1v[8] avar 2 rd g2v[7] g2v[6] g2v[5] g2v[4] g2v[3] g2v[2] g2v[1] g2v[0] avar 3 rd g2v[15] g2v[14] g2v[13] g2v[12] g2v[11] g2v[10] g2v[9] g2v[8] avar 4 rd g3v[7] g3v[6] g3v[5] g3v[4] g3v[3] g3v[2] g3v[1] g3v[0] avar 5 rd g3v[15] g3v[14] g3v[13] g3v[12] g3v[11] g3v[10] g3v[9] g3v[8] table 42. auxiliary register group b register rd/wr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 avbr 0 rd g4v[7] g4v[6] g4v[5] g4v[4] g4v[3] g4v[2] g4v[1] g4v[0] avbr 1 rd g4v[15] g4v[14] g4v[13] g4v[12] g4v[11] g4v[10] g4v[9] g4v[8] avbr 2 rd g5v[7] g5v[6] g5v[5] g5v[4] g5v[3] g5v[2] g5v[1] g5v[0] avbr 3 rd g5v[15] g5v[14] g5v[13] g5v[12] g5v[11] g5v[10] g5 v[9] g5v[8] avbr 4 rd ref[7] ref[6] ref[5] ref[4] ref[3] ref[2] ref[1] ref[0] avbr 5 rd ref[15] ref[14] ref[13] ref[12] ref[11] ref[10] ref[9] ref[8] table 43. status register group a register rd/wr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 star 0 rd soc[7] soc[6] soc[5] soc[4] soc[3] soc[2] soc[1] soc[0] star 1 rd soc[15] soc[14] soc[13] soc[12] soc[11] soc[10] soc[9] soc[8] star 2 rd itmp[7] itmp[6] itmp[5] itmp[4] itmp[3] itmp[2] itmp[1] itmp[0] star 3 rd itmp [15] itmp[14] itmp[13] itmp[12] itmp[11] itmp[10] itmp[9] itmp[8] star 4 rd va [7] va [6] va [5] va [4] va [3] va [2] va [1] va [0] star 5 rd va [15] va [14] va [13] va [12] va [11] va [10] va [9] va [8] table 44. status register group b register rd/wr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stbr0 rd vd[7] vd[6] vd[5] vd[4] vd[3] vd[2] vd[1] vd[0] stbr1 rd vd[15] vd[14] vd[13] vd[12] vd[11] vd[10] vd[9] vd[8] stbr2 rd c4ov c4uv c3ov c3 uv c2ov c2uv c1ov c1uv stbr3 rd c8ov c8uv c7ov c7uv c6ov c6uv c5ov c5uv stbr4 rd c12ov c12uv c11ov c11uv c10ov c10uv c9ov c9uv stbr5 rd rev[3] rev[2] rev[1] rev[0] rsvd rsvd muxfail thsd table 45. comm register group register rd/wr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 comm0 rd/wr icom0[3] icom0[2] icom0[1] icom0[0] d0[7] d0[6] d0[5] d0[4] comm1 rd/ wr d0[3] d0[2] d0[1] d0[0] fcom0[3] fcom0[2] fcom0[1] fcom0[0] comm2 rd/wr icom1[3] icom1[2] icom1[1] icom1[0] d1[7] d1[6] d1[5] d1[4] comm3 rd/wr d1[3] d1[2] d1[1] d1[0] fcom1[3] fcom1[2] fcom1[1] fcom1[0] comm4 rd/wr icom2[3] icom2[2] icom2[1] icom2[0] d2[7] d2[6] d2[5] d2[4] comm5 rd/wr d2[3] d2[2] d2[1] d2[0] fcom2[3] fcom2[2] fcom2[1] fcom2[0] operation
ltc 6804 -1/ ltc 6804 -2 51 680412f for more information www.linear.com/LTC6804-1 operation table 46. memory bit descriptions name description values gpiox gpiox pin control write: 0 -> gpiox pin pull-down on; 1-> gpiox pin pull-down off read: 0 -> gpiox pin at logic 0; 1 -> gpiox pin at logic 1 refon reference powered up 1 -> reference remains powered up until watchdog timeout 0 -> reference shuts down after conversions swtrd swten pin status (read only) 1 -> swten pin at logic 1 0 -> swten pin at logic 0 adcopt adc mode option bit adcopt : 0 -> selects modes 27khz, 7khz or 26hz with md[1:0] bits in adc conversion commands. 1 -> selects modes 14khz, 3khz or 2khz with md[1:0] bits in adc conversion commands. vuv undervoltage comparison voltage * comparison voltage = (vuv + 1) ? 16 ? 100v default: vuv = 0x000 vov overvoltage comparison voltage * comparison voltage = vov ? 16 ? 100v default: vuv = 0x000 dcc[x] discharge cell x x = 1 to 12 1 -> turn on shorting switch for cell x 0 -> turn off shorting switch for cell x (default) dcto discharge time out value dcto (write) 0 1 2 3 4 5 6 7 8 9 a b c d e f time (min) disabled 0.5 1 2 3 4 5 10 15 20 30 40 60 75 90 120 dcto (read) 0 1 2 3 4 5 6 7 8 9 a b c d e f time left (min) disabled or timeout 0 to 0.5 0.5 to 1 1 to 2 2 to 3 3 to 4 4 to 5 5 to 10 10 to 15 15 to 20 20 to 30 30 to 40 40 to 60 60 to 75 75 to 90 90 to 120 cxv cell x voltage* x = 1 to 12 16- bit adc measurement value for cell x cell voltage for cell x = cxv ? 100v cxv is reset to 0xffff on power-up and after clear command gxv gpio x voltage* x = 1 to 5 16- bit adc measurement value for gpiox voltage for gpiox = gxv ? 100v gxv is reset to 0xffff on power-up and after clear command ref 2nd reference voltage * 16- bit adc measurement value for 2nd reference voltage for 2nd reference = ref ? 100v normal range is within 2.980v to 3.020v soc sum of cells measurement* 16- bit adc measurement value of the sum of all cell voltages sum of all cells voltage = soc ? 100v ? 20 itmp internal die temperature * 16- bit adc measurement value of internal die temperature temperature measurement voltage = itmp ? 100v/7.5mv/c C 273c va analog power supply voltage* 16- bit adc measurement value of analog power supply voltage analog power supply voltage = va ? 100v normal range is within 4.5v to 5.5v vd digital power supply voltage* 16- bit adc measurement value of digital power supply voltage digital power supply voltage = va ? 100v normal range is within 2.7v to 3.6v cxov cell x overvoltage flag x = 1 to 12 cell voltage compared to vov comparison voltage 0 -> cell x not flagged for overvoltage condition. 1 -> cell x flagged cxuv cell x undervoltage flag x = 1 to 12 cell voltage compared to vuv comparison voltage 0 -> cell x not flagged for undervoltage condition. 1 -> cell x flagged rev revision code device revision code rsvd reserved bits read: read back value is always 0
ltc 6804 -1/ ltc 6804 -2 52 680412f for more information www.linear.com/LTC6804-1 operation name description values muxfail multiplexer self- test result read: 0 -> multiplexer passed self test 1 -> multiplexer failed self test thsd thermal shutdown status read: 0 -> thermal shutdown has not occurred 1 -> thermal shutdown has occurred thsd bit cleared to 0 on read of status register group b icomn initial communication control bits write i2c 0110 0001 0000 0111 start stop blank no transmit spi 1000 1001 1111 csb low csb high no transmit read i2c 0110 0001 0000 0111 start from master stop from master sda low between bytes sda high between bytes spi 0111 dn i 2 c/spi communication data byte data transmitted (received) to (from) i 2 c/spi slave device fcomn final communication control bits write i2c 0000 1000 1001 master ack master nack master nack + stop spi x000 1001 csb low csb high read i2c 0000 0111 1111 0001 1001 ack from master ack from slave nack from slave ack from slave + stop from master nack from slave + stop from master spi 1111 * voltage equations use the decimal value of registers, 0 to 4095 for 12 bits and 0 to 65535 for 16 bits. programming examples the following examples use a configuration of 3 stacked LTC6804-1 devices: s1, s2, s3. port a on device s1 is configured in spi mode (isomd pin low). port a on de- vices s2 and s3 is configured in isospi mode (isomd pin high). port b on s1 is connected to port a on s2. port b on s2 is connected to port a on s3. the microcontroller communicates to the stack through port a on s1. waking up serial interface 1. send a dummy byte. the activity on csb and sck will wake up the serial interface on device s1. 2. wait for the amount of time 3 ? t wake in order to power up all devices s1, s2 and s3. for large stacks where some devices may go to the idle state after waking, apply steps 3 and 4: 3. send a second dummy byte. 4. wait for the amount of time 3 ? t ready 5. send commands write configuration registers 1. pull csb low 2. send wrcfg command (0x00 0x01) and its pec (0x3d 0x6e) 3. send cfgr0 byte of device s3, then cfgr1(s3), cfgr5(s3), pec of cfgr0(s3) to cfgr5(s3) 4. send cfgr0 byte of device s2, then cfgr1(s2), cfgr5(s2), pec of cfgr0(s2) to cfgr5(s2) 5. send cfgr0 byte of device s1, then cfgr1(s1), cfgr5(s1), pec of cfgr0(s1) to cfgr5(s1) 6. pull csb high, data latched into all devices on rising edge of csb table 46. memory bit descriptions
ltc 6804 -1/ ltc 6804 -2 53 680412f for more information www.linear.com/LTC6804-1 operation calculation of serial interface time for sequence above: number of LTC6804-1s in daisy chain stack = n number of bytes in sequence (b): command: 2 (command byte) + 2 (command pec) = 4 data: 6 (data bytes) + 2 (data pec) per ltc6804 = 8 bytes per device b = 4 + 8 ? n serial port frequency per bit = f time = (1/f) ? b ? 8 bits/byte = (1/f) ? [4 + 8 ? n] ? 8 time for 3 ltc6804 example above, with 1 mhz serial port = (1/1e 6) ? (4 + 8 ? 3) ? 8 = 224s note: this time will remain the same for all write and read commands. read cell voltage register group a 1. pull csb low 2. send rdcva command (0x00 0x04) and its pec (0x07 0xc2) 3. read cvar 0 byte of device s1, then cvar 1(s 1), cvar 5(s1), pec of cvar0(s1) to cvar5(s1) 4. read cvar 0 byte of device s2, then cvar 1(s 2), cvar 5(s2), pec of cvar0(s2) to cvar0(s2) 5. read cvar 0 byte of device s3, then cvar 1(s 3), cvar 5(s3), pec of cvar0(s3) to cvar5(s3) 6. pull csb high start cell voltage adc conversion (all cells, normal mode with discharge permitted) and poll status 1. pull csb low 2. send adcv command with md[1:0] = 10 and dcp = 1 i.e. 0x03 0x70 and its pec (0xaf 0x42) 3. pull csb high clear cell voltage registers 1. pull csb low 2. send clrcell command (0x 07 0x11) and its pec (0xc9 0xc0) 3. pull csb high poll adc status (parallel configuration and isomd = 0) this example uses an addressed ltc6804-2 with address a [3:0] = 0011 and isomd = 0 1. pull csb low 2. send pladc command (0x9f 0x14) and its pec (0x1c 0x48 ) 3. sdo output is pulled low if the ltc6804-2 is busy. the host needs to send clocks on sck in order for the poll- ing status to be updated from the addressed device. 4. sdo output is high when the ltc6804-2 has completed conversions 5. pull csb high to exit polling talk to an i 2 c slave connected to ltc6804 the ltc6804 supports i 2 c slave devices by connection to gpio4(sda) and gpio5(scl). one valuable use for this capability is to store production calibration constants or other information in a small serial eeprom using a con- nection like shown in figure 25. figure 25. connecting i 2 c eeprom to ltc6804 gpio pins 680412 f25 gpio5(scl) gpio4(sda) 4.7k v ? v reg ltc6804 1f 10v 4.7k wp vcc 24aa01 scl vss sda
ltc 6804 -1/ ltc 6804 -2 54 680412f for more information www.linear.com/LTC6804-1 this example uses a single LTC6804-1 to write a byte of data to an i 2 c eeprom. the ltc6804 will send three bytes of data to the i 2 c slave device. the data sent will be b 0 = 0 xa 0 (eeprom address), b 1 = 0 x 01 (write com- mand), and b2 = 0 xaa (data to be stored in eeprom). the three bytes will be transmitted to the i 2 c slave device in the following format: start C b0 C nack C b1 C nack C b2 C nack C stop 1. write data to comm register using wrcomm command a . pull csb low b . send wrcomm command (0x07 0x21) and its pec (0x24 0xb2) c . send comm0 = 0x6a, comm1 = 0x08 ([ start] [b0 [nack]), comm2 = 0x00, comm3 = 0x18 ([blank] [b1] [nack]), comm4 = 0x0a, comm5 = 0xa9 ([blank] [b2] [nack+stop]) and pec = 0x6d 0xfb for the above data d . pull csb high 2. send the 3 bytes of data to i 2 c slave device using stcomm command a . pull csb low b . send stcomm command (0x07 0x23) and its pec (0xb9 0xe4) c . send 72 clock cycles on sck d . pull csb high 3. data transmitted to slave during the stcomm com- mand is stored in the comm register . use the rdcomm command to retrieve the data a . pull csb low b . send rdcomm command (0x 07 0x22) and its pec (0x32 0xd6) c . read comm0-comm5 and the pec for the 6 bytes of data. assuming the slave acknowledged all 3 bytes of data, the read back data in this example would look like: comm0 = 0x6a, comm1 = 0x07, comm2 = 0x70, comm3 = 0x17, comm4 = 0x7a, comm5 = 0xa1, pec = 0xd0 0xde d . pull csb high note: if the slave returns data, this data will be placed in commo-comm5. figure 26 shows the activity on gpio5 (scl) and gpio4 (sda) ports of the i 2 c master for 72 clock cycles during the stcomm command in the above example. figure 26. ltc6804 i 2 c communication example 680412 f26 sda (gpio4) scl (gpio5) start ack from slave 0xa0 0x01 0xaa sck stop last clock of stcomm command ack from slave ack from slave operation
ltc 6804 -1/ ltc 6804 -2 55 680412f for more information www.linear.com/LTC6804-1 talk to a spi slave connected to ltc6804 this example uses a single LTC6804-1 device which has a spi device connected to it through gpio3 (csbm), gpio4 (sdom) and gpio5 (sckm). in this example , the ltc6804 device sends out 3 bytes of data b 0 = 0 x55, b 1 = 0 xaa and b2 = 0xcc to the spi slave device in the following format: csb low C b0 C b1 C b2 C csb high 1. write data to comm register using wrcomm command a . pull csbm low b . send wrcomm command (0x07 0x21) and its pec (0x24 0xb2) c . send comm0 = 0x85, comm1 = 0x50 ([csbm low] [b0] [csbm low]), comm2 = 0x8a, comm3 = 0xa0 ([csbm low] [b1] [csbm low]), comm4 = 0x8c, comm5 = 0xc9 ([csbm low] [b2] [csbm high]) and pec = 0x89 0xa4 for the above data. d . pull csb high 2. send the 3 bytes of data to spi slave device using stcomm command a . pull csb low b . send stcomm command (0x07 0x23) and its pec (0xb9 0xe4) c . send 72 clock cycles on sck d . pull csb high 3. data transmitted to slave during the stcomm com- mand is stored in the comm register . use the rdcomm command to retrieve the data. a . pull csb low b . send rdcomm command (0x 07 0x22) and its pec (0x32 0xd6) c . read comm0-comm5 and the pec for the 6 bytes of data. the read back data in this example would look like: comm0 = 0x755f, comm1 = 0x7aaf, comm2 = 7ccf, pec = 0xf2ba d . pull csb high note: if the slave returns data, this data will be placed in comm0-comm5. figure 27 shows the activity on gpio 3 (csbm), gpio5 (sckm) and gpio4 (sdom) ports of spi master for 72 clock cycles during the stcomm command in the above example. operation figure 27. ltc6804 spi communication example 680412 f27 sdom (gpio4) sckm (gpio5) csbm low 0x55 0xaa 0xcc csbm (gpio3) sck csbm high last clock of stcomm command
ltc 6804 -1/ ltc 6804 -2 56 680412f for more information www.linear.com/LTC6804-1 applications information simple linear regulator the ltc6804 draws most of its power from the v reg input pin. 5v 0.5v should be applied to v reg . a regulated dc/ dc converter can power v reg directly, or the drive pin may be used to form a discrete regulator with the addition of a few external components. when active, the drive output pin provides a low current 5.6v output that can be buffered using a discrete npn transistor, as shown in figure 28. the collector power for the npn can come from any potential of 6v or more above v C , including the cells being monitored or an unregulated converter supply. a 100/100nf rc decoupling network is recommended for the collector power connection to protect the npn from transients . the emitter of the npn should be bypassed with a 1f capacitor. larger capacitor values should be avoided because they increase the wake-up time of the ltc6804. some attention to the thermal characteristic of the npn is needed, as there can be significant heating with a high collector voltage. the czt5551 shown is a sot-223 part that provides good design margin. figure 28. simple v reg power source using npn pass transistor figure 29. v reg powered from cell stack with high efficiency v in boost lt3990 sw en/uvlo pg rt 0.22f 22pf 374k f = 400khz 22f 2.2f v in 28v to 62v v reg 5v 40ma 1m 316k 1k 33h bd fb gnd off on 680412 f29 1f 0.1f 100 680412 f28 wdt drive v reg swten v ref1 v ref2 gpio5 gpio4 v ? v ? gpio3 1f 1f ltc6804 nsv1c201mz4 improved regulator power efficiency to minimize power consumption within the ltc6804, the current drawn on the v + pin has been designed to be very small (500a). the voltage on the v + pin must be at least as high as the top cell to provide accurate measurement. the v + and v reg pins can be unpowered to provide an exceptionally low battery drain shutdown mode. in many applications, the v + will be permanently connected to the top cell potential through a decoupling rc to protect against transients (100/100nf is recommended). for better running efficiency when powering from the cell stack, the v reg may be powered from a buck converter rather than the npn pass transistor. an ideal circuit for this is based on the lt3990 as shown in figure 29. a 1k resistor should be used in series with the input to prevent inrush current when connecting to the stack and to reduce conducted emi. the en/uvlo pin should be connected to drive so that the converter sleeps along with the ltc 6804 .
ltc 6804 -1/ ltc 6804 -2 57 680412f for more information www.linear.com/LTC6804-1 applications information fully isolated power a simple dc/dc flyback converter can provide isolated power for an ltc6804 from a remote 12v power source as shown in figure 30. this circuit , along with the isospi transformer isolation, results in ltc6804 circuitry that is completely floating and uses almost no power from the batteries. aside from reducing the amount of circuitry that operates at battery potential, such an arrangement prevents battery load imbalance. figure 31. typical temperature probe circuit and relative output temperature (c) ?40 0 v tempx (% v ref2 ) 100 80 60 40 20 90 70 50 30 10 0 ?20 20 6040 80 680412 f31 10k ntc 10k at 25c v ? v ref2 v temp figure 30. powering ltc6804 from a remote 12v source 680412 f30 drive v reg v ? v + ltc6804 100nf 100v cmhz5265b 62v nsv1c201mz4 cmhd459a pa0648nl cmmsh1-40 gnd en/uvlo r fb lt8300 130k 100 sw v in 1f 10v 4.7f 25v 7 2 8 1 5 4 1f 100v 22.1k 100k 12v 52v 13v 12v return 4.7f 25v ? ? ? reading external temperature probes figure 31 shows the typical biasing circuit for a negative- temperature-coefficient (ntc) thermistor. the 10k at 25c is the most popular sensor value and the v ref2 output stage is designed to provide the current required to directly bias several of these probes. the biasing re- sistor is selected to correspond to the ntc value so the circuit will provide 1.5v at 25c ( v ref2 is 3v nominal). the overall circuit response is approximately C1%/c in the range of typical cell temperatures, as shown in the chart of figure 31 .
ltc 6804 -1/ ltc 6804 -2 58 680412f for more information www.linear.com/LTC6804-1 figure 32. mux circuit supports sixteen additional analog measurements s0 s1 s2 s3 s4 s5 s6 s7 v cc scl sda a0 a1 gnd v ee d o analog1 analog2 analog3 analog4 analog5 analog6 analog7 analog8 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ltc1380 s0 s1 s2 s3 s4 s5 s6 s7 v cc scl sda a0 a1 gnd v ee d o analog9 analog10 analog11 analog12 analog13 analog14 analog15 analog16 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ltc1380 3 27 31 32 33 37 5 1f 10nf 680412 f32 v reg gpio5(scl) gpio4(sda) v ? gpio1 ltc6804 4.7k 4.7k 1 2 4 ? + ltc6255 100 analog inputs: 0.04v to 4.5v applications information expanding the number of auxiliary measurements the ltc6804 provides five gpio pins, each of which is capable of performing as an adc input. in some applica- tions there is need to measure more signals than this, so one means of supporting higher signal count is to add a mux circuit such as shown in figure 32. this circuit digitizes up to sixteen source signals using the gpio 1 adc input and mux control is provided by two other gpio lines configured as an i 2 c port. the buffer amplifier provides for fast settling of the selected signal to increase the usable conversion rate. internal protection features the ltc6804 incorporates various esd safeguards to en- sure a robust performance . an equivalent circuit showing the specific protection structures is shown in figure ?33. while pins 43 to 48 have different functionality for the -1 and -2 variants, the protection structure is the same. zener - like suppressors are shown with their nominal clamp voltage , other diodes exhibit standard pn junction behavior . filtering of cell and gpio inputs the ltc6804 uses a delta-sigma adc, which has delta- sigma modulator followed by a sinc3 finite impulse response (fir) digital filter. this greatly reduces input filtering requirements. furthermore, the programmable oversampling ratio allows the user to determine the best trade-off between measurement speed and filter cutoff frequency. even with this high order lowpass filter, fast transient noise can still induce some residual noise in mea- surements , especially in the faster conversion modes . this can be minimized by adding an rc lowpass decoupling to each adc input, which also helps reject potentially damag- ing high energy transients. adding more than about 100 to the adc inputs begins to introduce a systematic error in the measurement, which can be improved by raising the filter capacitance or mathematically compensating in software with a calibration procedure. for situations that demand the highest level of battery voltage ripple rejec- tion, grounded capacitor filtering is recommended. this configuration has a series resistance and capacitors that decouple hf noise to v C . in systems where noise is less
ltc 6804 -1/ ltc 6804 -2 59 680412f for more information www.linear.com/LTC6804-1 applications information 680412 f33 ltc6804 10k 12v c12 s12 12v 10k 12v c11 s11 12v 10k 12v c10 s10 12v 10k 12v c9 s9 12v 10k 12v c8 s8 12v 10k 12v c7 s7 12v 10k 12v c6 s6 12v 10k 12v c5 s5 12v 10k 12v c4 s4 12v 10k 12v c3 s3 12v 10k 12v c2 s2 12v 10k 12v 25 c1 s1 12v c0 v ? v ? 30v 30v 30v 30v 30v 30v gpio1 12v gpio2 12v gpio3 12v gpio4 gpio5 12v v ref2 12v 12v v ref1 12v swten 12v v reg 12v drive 12v wdt 12v isomd 12v csb 12v sck 12v sdi 12v sdo 12v ibias/a0 12v icmp/a1 12v imb/a2 12v ipb/a3 12v v + note: not shown are pn diodes to all other pins from pin 31 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 32 33 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 figure 33. internal esd protection structure of ltc6804 periodic or higher oversample rates are in use , a differential capacitor filter structure is adequate. in this configuration there are series resistors to each input, but the capacitors connect between the adjacent c pins. however, the dif- ferential capacitor sections interact. as a result, the filter response is less consistent and results in less attenuation than predicted by the rc, by approximately a decade. note that the capacitors only see one cell of applied voltage ( thus smaller and lower cost) and tend to distribute transient energy uniformly across the ic (reducing stress events on the internal protection structure). figure 34 shows the two methods schematically. basic adc accuracy varies with r, c as shown in the typical performance curves , but error is minimized if r = 100 and c = 10nf. the gpio pins will always use a grounded capacitor configuration because the measurements are all with respect to v C . figure 34. input filter structure configurations 680412 f34 cell2 v ? c2 10nf battery v ? 100 differential capacitor filter rqj0303 33 3.3k cell1 c1 s2 s1 ltc6804 ltc6804 s2 s1 10nf 10nf 100 rqj0303 33 100 c0 3.3k cell2 v ? c2 battery v ? 100 grounded capacitor filter rqj0303 33 3.3k * cell1 c1 100 rqj0303 *6.8v zeners recommended if c > 100nf 33 c0 c c c 3.3k * * 100
ltc 6804 -1/ ltc 6804 -2 60 680412f for more information www.linear.com/LTC6804-1 figure 35. internal discharge circuit figure 36. external discharge circuit applications information cell balancing with internal mosfets the s1 through s12 pins are used to balance battery cells. if one cell in a series becomes overcharged , an s output can be used to discharge the cell. each s output has an internal n-channel mosfet for discharging. the nmos has a maximum on resistance of 20. an external resistor should be connected in series with the nmos to dissipate heat outside of the ltc6804 package as illustrated in fig- ure 35. it is still possible to use an rc to add additional filtering to cell voltage measurements but the filter r must remain small, typically around 10 to reduce the effect on the programmed balance current. when using the internal mosfets to discharge cells, the die temperature should be monitored . see power dissipation and thermal shutdown section. cell balancing with external mosfets the s outputs include an internal pull-up pmos transistor. the s pins can act as digital outputs suitable for driving the gate of an external mosfet. for applications requiring high battery discharge currents, connect a discrete pmos switch device and suitable discharge resistor to the cell, and the gate terminal to the s output pin, as illustrated in figure 36. figure 34 shows external mosfet circuits that include rc filtering. table 47. discharge control during an adcv command with dcp = 0 cell measurement periods cell calibration periods cell1/7 cell2/8 cell3/9 cell4/10 cell5/11 cell6/12 cell1/7 cell2/8 cell3/9 cell4/10 cell5/11 cell6/12 discharge pin t 0 to t 1m t 1m to t 2m t 2m to t 3m t 3m to t 4m t 4m to t 5m t 5m to t 6m t 6m to t 1c t 1c to t 2c t 2c to t 3 c t 3c to t 4c t 4c to t 5c t 5c to t 6c s1 off off on on on off off off on on on off s2 off off off on on on off off off on on on s3 on off off off on on on off off off on on s4 on on off off off off on on off off off off s5 on on on off off off on on on off off off s6 off on on on off off off on on on off off s7 off off on on on off off off on on on off s8 off off off on on on off off off on on on s9 on off off off on on on off off off on on s10 on on off off off off on on off off off off s11 on on on off off off on on on off off off s12 off on on on off off off on on on off off ltc6804 680412 f35 r filter r filter r discharge c(n) s(n) c(n ? 1) + ltc6804 680412 f36 r rqj0303pgd 3.3k c(n) s(n) c(n ? 1) + discharge control during cell measurements if the discharge permited (dcp) command bit is high in a cell measurement command , then the s pin discharge states are not altered during the cell measurements. however, if the dcp bit is low, any discharge that is turned on will be turned off when the corresponding cell or adjacent cells are being measured. table 47 illustrates this during an
ltc 6804 -1/ ltc 6804 -2 61 680412f for more information www.linear.com/LTC6804-1 applications information adcv command with dcp = 0. in this table, off implies that a discharge is forced off during that period even if the corresponding dcc[x] bit is high in the configuration register. on implies that if the discharge is turned on, it will stay on during that period. refer to figure 3 for the timing of the adcv command. power dissipation and thermal shutdown the internal mosfets connected to the pins s1 through s12 pins can be used to discharge battery cells. an exter - nal resistor should be used to limit the power dissipated by the mosfets . the maximum power dissipation in the mosfets is limited by the amount of heat that can be tol- erated by the ltc6804. excessive heat results in elevated die temperatures. little or no degradation will be observed in the measurement accuracy for die temperatures up to 125c. damage may occur above 150c, therefore the recommended maximum die temperature is 125c. to protect the ltc6804 from damage due to overheating a thermal shutdown circuit is included. overheating of the device can occur when dissipating significant power in the cell discharge switches. the thermal shutdown circuit is enabled whenever the device is not in sleep mode (see modes of operation). if the temperature detected on the device goes above approximately 150c the configura- tion registers will be reset to default states turning off all discharge switches. when a thermal shutdown has occurred, the thsd bit in the status register group b will go high. the bit is cleared after a read operation of the status register group b. the bit can also be set using the clrstat command. since thermal shutdown interrupts normal operation, the internal temperature monitor should be used to determine when the device temperature is ap- proaching unacceptable levels. method to verify balancing circuitry the functionality of the discharge circuitry is best verified by cell measurements. figure 37 shows an example using the ltc6804 battery monitor ic. the resistor between the battery and the source of the discharge mosfet causes cell voltage measurements to decrease. the amount of measurement change depends on the resistor values and the mosfet on resistance. the following algorithm could be used in conjunction with figure 37: 1. measure all cells with no discharging (all s outputs off) and read and store the results. 2. turn on s1 and s7 3. measure c1-c0, c7-c6 4. turn off s1 and s7 5. turn on s2 and s8 6. measure c2-c1, c8-c7 7. turn off s2 and s8 14. turn on s6 and s12 15. measure c6-c5, c12-c11 16. turn off s6 and s12 17. read the voltage register group to get the results of steps 2 thru 16. 18. compare new readings with old readings. each cell voltage reading should have decreased by a fixed percentage set by r b1 and r b2 (figure 37). the exact amount of decrease depends on the resistor values and mosfet characteristics. improved pec calculation the pec allows the user to have confidence that the serial data read from the ltc6804 is valid and has not been corrupted by any external noise source. this is a critical feature for reliable communication and the ltc 6804 requires that a pec be calculated for all data being read from and written to the ltc6804. for this reason it is important to have an efficient method for calculating the pec. the code below demonstrates a simple implementation of a lookup table derived pec calculation method. there are two functions , the first function init _ pec15_table () should only be called once when the microcontroller starts and will initialize a pec15 table array called pec15table[]. this table will be used in all future pec calculations. the pec15 table can also be hard coded into the microcontroller rather than running the init_pec15_ table() function at startup. the pec15() function calculates the pec and will return the correct 15 bit pec for byte arrays of any given length.
ltc 6804 -1/ ltc 6804 -2 62 680412f for more information www.linear.com/LTC6804-1 applications information figure 37. balancing self test circuit 680412 f37 v + c12 s12 c11 s11 c10 s10 c9 s9 c8 s8 c7 s7 c6 s6 c5 s5 c4 s4 c3 s3 c2 s2 c1 v ? c0 s1 ltc6804 r b1 r b1 r b2 r b1 r b2 r b1 r b2 r b1 r b2 r b1 r b2 r b1 r b2 r b1 r b2 r b1 r b2 r b1 r b2 r b1 r b2 r b1 r b2 r b2
ltc 6804 -1/ ltc 6804 -2 63 680412f for more information www.linear.com/LTC6804-1 applications information /************************************ copyright 2012 linear technology corp. (ltc) permission to freely use, copy, modify , and distribute this software for any purpose with or without fee is hereby granted , provided that the above copyright notice and this permission notice appear in all copies : this software is provided as is and ltc disclaims all warranties including all implied warranties of merchantability and fitness . in no event shall ltc be liable for any special , direct , indirect , or consequential damages or any damages whatsoever resulting from any use of same, including any loss of use or data or profits , whether in an action of contract , negligence or other tortuous action , arising out of or in connection with the use or performance of this software . ***********************************************************/ int16 pec15table[256]; int16 crc15_poly = 0x4599; void init_pec15_table() { for (int i = 0; i < 256; i++) { remainder = i << 7; for (int bit = 8; bit > 0; -- bit) { if (remainder & 0x4000) { remainder = ((remainder << 1)); remainder = (remainder ^ crc15poly) } else { remainder = ((remainder << 1)); } } pec15table[i] = remainder &0xffff; } } unsigned int16 pec15 (char *data , int len) { int16 remainder ,address ; remainder = 16;// pec seed for (int i = 0; i < len; i++) { address = ((remainder >> 7) ^ data[i]) & 0 xff;//calculate pec table address remainder = (remainder << 8 ) ^ pec15table[address ]; } return (remainder *2);// the crc15 has a 0 in the lsb so the final value must be multiplied by 2 }
ltc 6804 -1/ ltc 6804 -2 64 680412f for more information www.linear.com/LTC6804-1 applications information figure 38. interfacing a typical hall-effect battery current sensor to auxiliary adc inputs current measurement with a hall effect sensor the ltc6804 auxiliary adc inputs (gpio pins) may be used for any analog signal, including those from various active sensors that generate a compatible voltage. one such example that may be useful in a battery management setting is the capture of battery current . hall - effect sensors are popular for measuring large battery currents since the technology provides a non-contact, low power dissipation solution. figure 38 shows schematically a typical hall sensor that produces two outputs that proportion to the v cc provided. the sensor is powered from a 5v source and produces analog outputs that are connected to gpio pins or inputs of the mux application shown in figure 32. the use of gpio 1 and gpio2 as the adc inputs has the possibility of being digitized within the same conversion sequence as the cell inputs (using the adcvax com- mand), thus synchronizing cell voltage and cell current measurements. current measurement with a shunt resistor it is possible to measure the battery current on the ltc 6804 gpio pins with a high performance current sense ampli- fier and a shunt. figure 39 shows 2 ltc 6102s being used to measure the discharge and charge currents on a 12-cell battery stack. to achieve a large dynamic range while maintaining a high level of accuracy the ltc6102 is required. the circuit shown is able to accurately mea- sure 200amps to 0.1amps. the offset of the ltc6102 will only contribute a 20ma error. to maintain a very low sleep current the v drive is used to disable the ltc6102 circuits so that they draw no current when the ltc6804 goes to sleep. 680412 f38 lem dhab ch2 analog gpio2 v cc 5v gnd analog_com v ? ch1 analog0 gpio1 a b c d figure 39. monitoring charge and discharge currents with a ltc6102 charger ? + ? + + ? + ? l o a d v out d = i discharge ? r sense ( ) when i discharge 0 discharging: r out(d) r in(d) v out c = i charge ? r sense ( ) when i charge 0 charging: r out(c) r in(c) 680412 f39 v battstack r in(d) 100 ltc6102 ltc6804 v ? ltc6804 v ? v drive v drive r in(c) 100 r in(d) 100 ltc6102 ltc6804 v + v out(c) r out(c) 4.02k r out(d) 4.02k v out(d) gpio 1 gpio 2 r in(c) 100 i charge r sense 0.5m i discharge v + v ? out ?ins +in v + v ? out ?ins +in ?inf ?inf v reg 0.1f v reg 0.1f 1f 1f
ltc 6804 -1/ ltc 6804 -2 65 680412f for more information www.linear.com/LTC6804-1 applications information 680412 f40 v + c12 s12 c11 s11 c10 s10 c9 s9 c8 s8 c7 s7 c6 s6 c5 s5 c4 s4 c3 s3 c2 s2 c1 s1 c0 v ? ltc6804 + + + + + + + + next higher group of 8 cells next lower group of 8 cells using the ltc6804 with less than 12 cells if the ltc6804 is powered by the battery stack, the minimum number of cells that can be monitored by the ltc6804 is governed by the supply voltage requirements of the ltc6804. the sum of the cell voltages must be at least 11v to properly bias the ltc6804. figure 40 shows an example of the ltc6804 when used to monitor eight cells with best cell measurement synchronization. the 12 cells monitored by the ltc6804 are split into two groups of 6 cells and are measured using two internal multiplexers and two adcs. to optimize measurement synchronization in applications with less than 12 cells the unused c pins should be equally distributed between the top of the second figure 40. 8 cell connection scheme mux (c12) and the top of the first mux (c6). if there are an odd number of cells being used, the top mux should have fewer cells connected. the unused cell channels should be tied to the other unused channels on the same mux and then connected to the battery stack through a 100 resistor. the unused inputs will result in a reading of 0v for those cells channels. it is also acceptable to connect in the conventional sequence with all unused cell inputs at the top. connecting multiple LTC6804-1 on the same pcb when connecting multiple LTC6804-1 devices on the same pcb, only a single transformer is required between the ltc6804 - 1 isospi ports. with multiple LTC6804-1 devices on the same pcb , the noise rejection requirements are significantly lower and the isolation requirements are simplified. for this reason, a single transformer should be adequate to provide the required isolation and noise rejec- tion between ics on the battery stack. figure 41 shows an example application that has multiple LTC6804-1s on the same pcb, communicating to the bottom mcu through a ltc6820. connecting a mcu to an LTC6804-1 with an isospi d ata link a separate device, the ltc6820, will convert standard 4-wire spi into a 2-wire isospi link that can communi- cate directly with the ltc6804. an example is shown in figure ?42. the ltc6820 can be used in applications to easily provide isolation between the controller and the stack of ltc6804s. the ltc6820 also enables system configurations that have the bms controller at a remote location relative to the ltc6804 ics and the battery pack. configuring the ltc6804-2 in a multi-drop isospi link the addressing feature of the ltc6804-2 allows multiple devices to be connected to a single isospi master by multi-dropping them along one twisted pair essentially creating a large parallel spi network. an example multi- drop system is shown in figure 43 , the twisted pair should be terminated only at the beginning (master) and
ltc 6804 -1/ ltc 6804 -2 66 680412f for more information www.linear.com/LTC6804-1 applications information figure 41. connecting multiple LTC6804-1 devices on the same pcb figure 42. interfacing an LTC6804-1 with an ltc6820 for isolated spi control 120 ?? 120 2.8k 1.21k ipb imb ipa ibias icmp LTC6804-1 to next LTC6804-1 v ? ima 120 ?? ?? 120 120 5v 5v 5v 1.21k 5v 100nf 2.8k 1.21k 100nf 2.8k 1.21k 680412 f41 ipb imb ipa ibias icmp LTC6804-1 v ? ima ibias icmp gnd slow mstr ip im v dd sdo sdi sck cs v dds en mosi miso sck cs pol pha ltc6820 c 120 120 2.8k 1.21k 2.8k 1.21k 1.21k 100nf ibias icmp gnd slow mstr ip im v dd v dds en mosi miso sck cs pol pha 5v 5v 5v 5v ltc6820 100nf ipa ibias ima v ? icmp 680412 f42 LTC6804-1 to next LTC6804-1 120 ipb imb c sdo cs sdi sck ?? ?? ??
ltc 6804 -1/ ltc 6804 -2 67 680412f for more information www.linear.com/LTC6804-1 applications information 2.8k 1.21k ipa ibias isomd ima v ? v regb icmp ltc6804-2 2.8k 1.21k ipa ibias isomd ima v ? v rega icmp 680412 f43 ltc6804-2 2.8k 1.21k gndb gnda gndc gndb gnda gndc ipa ibias isomd ima v ? v regc icmp ltc6804-2 120 ?? ?? ?? ?? 120 2.8k 1.21k 1.21k 100nf ibias icmp gnd slow mstr ip im v dd v dds en mosi miso sck cs pol pha 5v 5v 5v 5v ltc6820 100nf c sdo cs sdi sck figure 43. connecting the ltc6804-2 in a multi-drop configuration the end. in between, the additional ltc6804-2s will be connected to stubs on the twisted pair. these stubs should be kept short, with as little capacitance as possible, to avoid degrading the termination along the isospi wiring. when a ltc6804-2 is not addressed, it will not transmit data pulses. this eliminates the possibility for collisions, as only the addressed device will ever be returning data to the master. the standard filtering circuits and layout guidelines outlined in the emc section should be followed in multi drop networks. transformer selection guide as shown in figure 44, a transformer or a pair of trans- formers are used to isolate the isospi signals between two isospi ports. the isospi signals have programmable pulse amplitudes up to 1.6v and pulse widths of 50ns and 150ns. to meet these requirements, choose a transformer having a magnetizing inductance ranging from 50h to 350h, and a 1:1 turns ratio. minimizing transformer in- sertion loss will reduce required transmit power; generally an insertion loss of less than C1.5db is recommended. to optimize common mode noise rejection, choose a center tapped transformer or a transformer with an integrated common mode choke as show in figure 45. the center tap should be tied to a 27pf or smaller capacitor (larger will restrict the drivers ability to set the common mode voltage). if the transformer has both a center tap and common mode choke on the primary side, a larger 100pf capacitor may be used . table 48 shows a recommended list of transformers for use with the ltc6804. 10/100basetx ethernet transformers are inexpensive and work very well in this application. ethernet transformers have an added benefit in that they normally have common mode chokes built in improving their common mode rejection versus other transformers.
ltc 6804 -1/ ltc 6804 -2 68 680412f for more information www.linear.com/LTC6804-1 applications information figure 44. isospi circuit table 47. recommended transformers manufacturer part number isolation voltage turns ratio temperature range cm choke center tap halo tg110-aex50n5lf 1500v rms 1:1 C45c to 125c yes yes halo tg110-ae050n5lf 1500v rms 1:1 C45c to 85c yes yes halo tgr01-6506v6nl 3000v rms 1:1 C40c to 105c no no pulse pe-68386nl 1500vdc 1:1 C40c to 130c no no pulse hx1188nl 1500v rms 1:1 C40c to 85c yes yes wrth 7490100111 1500v rms 1:1 C40c to 105c yes yes wrth 750340848 3750 v rms 1:1 C40c to 105c no no figure 46. capacitor isolation barrier figure 45. transformer with common mode choke r m ipa isomd v reg ima ibias icmp 680412 f44 ltc6804 r m r b1 r b2 r b1 r b2 ipb isomd imb ibias icmp mosi miso sck cs sdo sdi sck cs ltc6804 twisted-pair cable with characteristic impedance r m isolation barrier (may use one or two tranformers) master ?? ?? capacitive isolation barrier in some applications two ltc6804s can be monitoring the same group of batteries for redundancy or two strings of batteries connected in parallel. in these applications both of the ltc6804s will be at the same common mode voltage so the high cmrr of the transformers may not be required. in this situation an alternative to transform- ers is to use capacitors as the isolation barrier. the use of capacitors is suitable for low cost, isolated signaling over short distances (1 meter or less) that do not require high noise rejection. the capacitors will provide galvanic isolation, but no common mode rejection. this option uses the drivers in a different way, by using pull up resistors to maintain the common mode voltage near v reg , only the sinking drive current has any effect. figure 46 shows an example circuit using a capacitive isolation barrier capable of driving 1 meter of cable. 680412 f45 500 ipa isomd v reg ima 680412 f46 ltc6804 500 500 500 ipb isomd imb mosi miso sck cs sdo sdi sck cs ltc6804 c 100nf 100nf v reg isospi setup the ltc6804 allows the isospi link in each application to be optimized for power consumption or for noise immunity . the power and noise immunity of an isospi system is determined by the programmed i b current. the i b current can range from 100a to 1ma. a low i b reduces the isospi power consumption in the ready and active states , while a high i b increases the amplitude of the differential signal
ltc 6804 -1/ ltc 6804 -2 69 680412f for more information www.linear.com/LTC6804-1 applications information voltage v a across the matching termination resistor, r m . i b is programmed by the sum of the r b1 and r b2 resistors connected between the ibias pin and gnd as shown in figure 44. for most applications setting i b to 0.5ma is a good compromise between power consumption and noise immunity. using this i b setting with a 1:1 transformer and r m = 120, r b1 should be set to 2.8k and r b2 set to 1.2k. in a typical cat 5 twisted pair these settings will allow for communication up to 50m. for applications that require cables longer than 50m it is recommended to increase the i b to 1ma. this compensates for the increased insertion loss in the cable and maintains high noise immunity. so when using cables over 50m and, again, using a trans- former with a 1:1 turns ratio and r m =?120, r b1 would be 1.4k and r b2 would be 600. other i b settings can be used to reduce power consumption or increase the noise immunity as required by the application. in these cases when setting threshold voltage v icmp and choosing r b1 and r b2 resistor values the following rules should be used: for cables under 50m : i b = 0.5ma v a = (20 ? i b ) ? (r m /2) v tcmp = ? ? v a v icmp = 2 ? v tcmp r b2 = v icmp /i b r b1 = (2/i b ) C r b2 for cables over 50m: i b = 1ma v a = (20 ? i b ) ? (r m /2) v tcmp = 1/4 ? v a v icmp = 2 ? v tcmp r b2 = v icmp /i b r b1 = (2/i b ) C r b2 the maximum data rate of an isospi link is determined by the length of the cable used. for cables 10 meters or less the maximum 1mhz spi clock frequency is possible. as the length of the cable increases the maximum possible spi clock rate decreases. this is a result of the increased propagation delays through the cable creating possible timing violations. figure 47 shows how the maximum data rate is reduced as the cable length increases when using a cat 5 twisted pair. cable delay affects three timing specifications, t clk , t 6 and t 7 . in the electrical characteristics table, each is derated by 100ns to allow for 50ns of cable delay. for longer cables, the minimum timing parameters may be calculated as shown below: t clk , t 6 and t 7 > 0.9s + 2 ? t cable emc for the best electromagnetic compatibility (emc) per - formance, it is recommended to use one of the circuits in figures 48 and 49. the center tap of the transformer should be bypassed with a 100pf capacitor. the center tap capacitor will help attenuate common mode signals. large center tap capacitors greater than 100pf should be avoided as they will prevent the isospi transmitters com- mon mode voltage from settling. if a transformer without a center tap is used, the termination resistor should be split into two equal halves and connected in series across the ip and dm lines. the center of the two resistors should be bypassed with a capacitor as shown in figure 49. to improve common mode current rejection a common mode choke should also be placed in series with the ip and im lines of the ltc6804. the common mode choke will both increase emi immunity and reduce emi emission. when choosing a common mode choke, the differential mode impedance should be 20 or less for signals 50mhz and below. common mode chokes similar to what is used in ethernet applications are recommended. figure 47. data rate vs cable length cable length (meters) 1 data rate (mbps) 1.2 0.8 0.4 0.2 1.0 0.6 0 10 680412 f47 100 cat-5 assumed
ltc 6804 -1/ ltc 6804 -2 70 680412f for more information www.linear.com/LTC6804-1 figure 48. recommended isospi circuit for best emc performance figure 49. recommended isospi circuit for best emc performance when using a transformer without a center tap layout of the isospi signal lines also plays a significant role in maximizing the immunity of a circuit . the following layout guidelines should be followed: 1. the transformer should be placed as close to the isospi cable connector as possible. the distance should be kept less than 2cm. the ltc6804 should be placed at least 1cm to 2cm away from the transformer to help isolate the ic from magnetic field coupling. 2. on the top component layer, no ground plane should be placed under the transformer, the isospi connector, or in between the transformer and the connector. 3. the isospi signal traces should be isolated from sur - rounding circuits and traces by ground metal or space. no traces should cross the isospi signal lines, unless separated by a ground plane on an inner layer. the isospi drive currents are programmable and allow for a trade-off between power consumption and noise immunity. the noise immunity of the ltc6804 has been evaluated using a bulk current injection (bci) test. the bci test injects current into the twisted-pair lines at set levels over a frequency range of 1mhz to 400mhz. with the minimum i b current, 100a, the isospi serial link was capable of passing a 40ma bci test with no bit errors. a 40ma bci test level is sufficient for industrial applications. automotive applications have a much higher bci require- ment so the ltc 6804 ib is set to 1 ma , the maximum power level. the isospi system is capable of passing a 200ma bci test with no transmitted bit errors. the 200ma test level is typical for automotive requirements. 680412 f48 transformer with common mode choke 100pf 120 ip im ltc6804 60.4 100pf common mode choke 60.4 680412 f51 ltc6804 ip im table 49. recommended common mode chokes manufacturer part number tdk act45b-220-2p murata d lw 43sh510xk2 applications information
ltc 6804 -1/ ltc 6804 -2 71 680412f for more information www.linear.com/LTC6804-1 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 0.10 ? 0.25 (.004 ? .010) 0 ? 8 g48 (ssop) 0910 rev 0 seating plane 0.55 ? 0.95** (.022 ? .037) 1.25 (.0492) ref 5.00 ? 5.60* (.197 ? .221) 7.40 ? 8.20 (.291 ? .323) 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 21 22 23 24 13 4445464748 43 42 41 40 39 38 37 36 35 34 33 31 30 29 28 27 26 25 32 12.50 ? 13.10* (.492 ? .516) 2.0 (.079) max 1.65 ? 1.85 (.065 ? .073) 0.05 (.002) min 0.50 (.01968) bsc 0.20 ? 0.30 ? (.008 ? .012) typ millimeters (inches) dimensions do not include mold flash or protrusions, but do include mold mismatch and are measured at the parting line. mold flash shall not exceed .15mm per side length of lead for solderring to a substrate the maximum dimension does not include dambar protrusions. dambar protrusions do not exceed 0.13mm per side * ** ? note: 1.drawing is not a jedec outline 2. controlling dimension: millimeters 3. dimensions are in 4. drawing not to scale 5. formed leads shall be planar with respect to one another within 0.08mm at seating plane 0.25 0.05 parting line 0.50 bsc 5.3 ? 5.7 7.8 ? 8.2 recommended solder pad layout apply solder mask to areas that are not soldered 1.25 0.12 g package 48-lead plastic ssop (5.3mm) (reference ltc dwg # 05-08-1887 rev ?)
ltc 6804 -1/ ltc 6804 -2 72 680412f for more information www.linear.com/LTC6804-1 ? linear technology corporation 2013 lt 0413 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/LTC6804-1 related parts typical application part number description comments ltc6801 independent multicell battery stack fault monitor monitors up to 12 series-connected battery cells for undervoltage or overvoltage . companion to ltc6802, ltc6803 and ltc6804 ltc6802 precision multicell battery stack monitor 1st generation: superseded by the ltc6804 and ltc6803 for new designs ltc6803 precision multicell battery stack monitor 2nd generation: functionally enhanced and pin compatible to the ltc6802 ltc6820 isolated bidirectional communications interface for spi provides an isolated interface for spi communication up to 100 meters, using a twisted pair. companion to the ltc6804 ltc3300 high efficiency bidirectional multicell battery balancer bidirectional synchronous flyback balancing of up to 6 li-ion or lifep04 cells in series. up to 10a balancing current (set by external components). bidirectional architecture minimizes balancing time and power dissipation. up to 92% charge transfer efficiency. 48-lead exposed pad qfn and lqfp packages basic 12-cell monitor with isospi daisy chain 680412 ta02 v + c12 s12 c11 s11 c10 s10 c9 s9 c8 s8 c7 s7 c6 s6 c5 s5 c4 s4 c3 s3 c2 s2 c1 ipb imb icmp ibias sdo (nc) sdi (nc) sck (ipa) csb (ima) isomd wdt drive v reg swten v ref1 v ref2 gpio5 gpio4 v ? v ? gpio3 gpio2 gpio1 c0 s1 LTC6804-1 10 7 6 8 9 11 isospia ? isospi port a tg110-ae050n5* isospia + 2 1 806 1.2k cell2 3.6v 10nf 100 rqj0303 33 3.3k cell1 3.6v cell3 3.6v 10nf 100 rqj0303 33 3.3k + + + cell12 3.6v 10nf 100 rqj0303 33 100 100 3.3k cell11 3.6v 100 cell3 to cell11 circuits 1f 100nf 100nf 1f 1f 120 15 2 1 3 14 16 isospib ? isospi port b isospib + 2 1 120 27pf *the part shown is a dual transformer with built-in common mode chokes 27pf ?? ?? + + nsv1c201mz4

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